D2-45057 Просмотр технического описания (PDF) - Renesas Electronics
Номер в каталоге
Компоненты Описание
Список матч
D2-45057 Datasheet PDF : 30 Pages
| |||
D2-45057, D2-45157
Absolute Maximum Ratings (Note 7)
Supply Voltage
HVDD[A:D], VDDHV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +28.0V
RVDD, PWMVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 4.0V
CVDD, PLLVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.4V
Input Voltage
Any Input but XTALI . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to RVDD +0.3V
XTALI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to PLLVDD +0.3V
Input Current, Any Pin but Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . ±10mA
Thermal Information
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
68 Ld QFN Package (Notes 5, 6) . . . . . . . .
25
1
Maximum Storage Temperature. . . . . . . . . . . . . . . . . . . . -55°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +85°C
High Voltage Supply Voltage,
HVDD[A:D], VDDHV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.0V to 26.5V
Digital I/O Supply Voltage, PWMVDD . . . . . . . . . . . . . . . . . . . . . . . . . . .3.3V
Core Supply Voltage, CVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.8V
Analog Supply Voltage, PLLVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.8V
Minimum Load Impedance (HVDD[A:D] ≤24.0V), ZL . . . . . . . . . . . . . . . . 4Ω
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
5. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
6. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
7. Absolute Maximum parameters are not tested in production.
Electrical Specifications TA = +25°C, HVDD[A:D]/VDDHV = 24V, CVDD = PLLVDD = 1.8V ±5%, RVDD = PWMVDD = 3.3V ±10%.
All grounds at 0.0V. All voltages referenced to ground. PLL at 294.912MHz, OSC at 24.576MHz, core running at 147.456MHz with typical audio data
traffic.
PARAMETER
TEST
CONDITIONS
SYMBOL
MIN
TYP
MAX UNIT
Digital Input High Logic Level (Note 8)
Digital Input Low Logic Level (Note 8)
High Level Output Drive Voltage
(IOUT at -Pin Drive Strength Current)
Low Level Output Drive Voltage
(IOUT at +Pin Drive Strength Current)
High Level Input Drive Voltage XTALI Pin
Low Level Input Drive Voltage XTALI Pin
Input Leakage Current (Note 9)
Input Capacitance
VIH
2
VIL
-
VOH
RVDD - 0.4
VOL
-
VIHX
0.7
VILX
-
IIN
-
Cin
-
-
-
V
-
0.8
V
-
-
V
-
0.4
V
-
PLLVDD V
-
0.3
V
-
±10 µA
9
-
pF
Output Capacitance
All Outputs Except
COUT
-
OUT[A:D]
9
-
pF
OUT[A:D]
-
190
-
pF
nRESET Pulse Width
Internal Pull-Up Resistance to PWMVDD
(for nERROR0-3, OCFG, nPDN)
tRST
-
10
-
ns
-
-
100
-
kΩ
Digital I/O Supply Pin Voltage, Current
Active Current
RVDD
3
and
PWMVDD
-
Power-Down Current
-
3.3
10
0.01
3.6
V
-
mA
-
mA
Core Supply Pins
CVDD
1.7
1.8
1.9
V
Active Current
-
300
-
mA
Power-Down Current
(Note 10)
-
6
-
mA
FN6785 Rev 1.00
May 5, 2016
Page 4 of 30
Share Link: 