Figures
Figure 1.1
Figure 1.2
Figure 1.3
Figure 2.1
Figure 2.2
Figure 2.3
Figure 2.4
Figure 2.5
Figure 2.6
Figure 2.7
Figure 2.8
Figure 2.9
Figure 2.10
Figure 2.11
Figure 2.12
Figure 2.13
Figure 2.14
Figure 2.15
Figure 2.16
Figure 2.17
Figure 2.18
Figure 3.1
Figure 3.2
Figure 4.1
Figure 4.2
Figure 4.3
Figure 4.4
Figure 4.5
Figure 4.6
Figure 4.7
Figure 5.1
Figure 5.2
Figure 5.3
Figure 5.4
Figure 5.5
Figure 5.6
xiv
Block Diagram...................................................................................................... 6
Pin Arrangement of H8/3024F-ZTAT, H8/3026F-ZTAT,
H8/3024 Mask ROM Version, and H8/3026 Mask ROM Version
(FP-100B or TFP-100B Package, Top View) ...................................................... 8
Pin Arrangement of H8/3024F-ZTAT, H8/3026F-ZTAT,
H8/3024 Mask ROM Version, and H8/3026 Mask ROM Version
(FP-100A Package, Top View) ............................................................................ 9
CPU Operating Modes ......................................................................................... 20
Memory Map........................................................................................................ 21
CPU Registers ...................................................................................................... 22
Usage of General Registers .................................................................................. 23
Stack ..................................................................................................................... 24
General Register Data Formats ............................................................................ 26
General Register Data Formats ............................................................................ 27
Memory Data Formats.......................................................................................... 28
Instruction Formats .............................................................................................. 41
Memory-Indirect Branch Address Specification.................................................. 45
Processing States .................................................................................................. 49
Classification of Exception Sources..................................................................... 50
State Transitions ................................................................................................... 51
Stack Structure after Exception Handling ............................................................ 52
On-Chip Memory Access Cycle .......................................................................... 54
Pin States during On-Chip Memory Access (Address Update Mode 1).............. 54
Access Cycle for On-Chip Supporting Modules.................................................. 55
Pin States during Access to On-Chip Supporting Modules.................................. 55
Memory Map of H8/3024F-ZTAT and H8/3024 Mask ROM Version
in Each Operating Mode ...................................................................................... 65
Memory Map of H8/3026F-ZTAT and H8/3026 Mask ROM Version
in Each Operating Mode ...................................................................................... 67
Exception Sources ................................................................................................ 70
Reset Sequence (Modes 1 and 3).......................................................................... 73
Reset Sequence (Modes 2 and 4).......................................................................... 74
Reset Sequence (Mode 6)..................................................................................... 75
Interrupt Sources and Number of Interrupts ........................................................ 76
Stack after Completion of Exception Handling.................................................... 77
Operation when SP Value is Odd......................................................................... 79
Interrupt Controller Block Diagram ..................................................................... 82
Block Diagram of Interrupts IRQ0 to IRQ5 .......................................................... 92
Timing of Setting of IRQnF ................................................................................. 93
Process Up to Interrupt Acceptance when UE = 1 ............................................... 98
Interrupt Masking State Transitions (Example) ................................................... 100
Process Up to Interrupt Acceptance when UE = 0 ............................................... 101