HD6433024F Просмотр технического описания (PDF) - Hitachi -> Renesas Electronics
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HD6433024F Datasheet PDF : 824 Pages
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14.1.1 Features ................................................................................................................. 429
14.1.2 Block Diagram ...................................................................................................... 430
14.1.3 Pin Configuration .................................................................................................. 431
14.1.4 Register Configuration .......................................................................................... 432
14.2 Register Descriptions.......................................................................................................... 432
14.2.1 A/D Data Registers A to D (ADDRA to ADDRD) .............................................. 432
14.2.2 A/D Control/Status Register (ADCSR) ................................................................ 433
14.2.3 A/D Control Register (ADCR).............................................................................. 435
14.3 CPU Interface ..................................................................................................................... 436
14.4 Operation ............................................................................................................................ 438
14.4.1 Single Mode (SCAN = 0)...................................................................................... 438
14.4.2 Scan Mode (SCAN = 1) ........................................................................................ 440
14.4.3 Input Sampling and A/D Conversion Time .......................................................... 442
14.4.4 External Trigger Input Timing .............................................................................. 443
14.5 Interrupts ............................................................................................................................ 444
14.6 Usage Notes........................................................................................................................ 444
Section 15 D/A Converter .................................................................................................. 449
15.1 Overview ............................................................................................................................ 449
15.1.1 Features ................................................................................................................. 449
15.1.2 Block Diagram ...................................................................................................... 450
15.1.3 Pin Configuration .................................................................................................. 451
15.1.4 Register Configuration .......................................................................................... 451
15.2 Register Descriptions.......................................................................................................... 452
15.2.1 D/A Data Registers 0 and 1 (DADR0, DADR1) .................................................. 452
15.2.2 D/A Control Register (DACR).............................................................................. 452
15.2.3 D/A Standby Control Register (DASTCR)........................................................... 454
15.3 Operation ............................................................................................................................ 454
15.4 D/A Output Control............................................................................................................ 456
Section 16 RAM.................................................................................................................... 457
16.1 Overview ............................................................................................................................ 457
16.1.1 Block Diagram ...................................................................................................... 458
16.1.2 Register Configuration .......................................................................................... 458
16.2 System Control Register (SYSCR) .................................................................................... 459
16.3 Operation ............................................................................................................................ 460
Section 17 Flash Memory [H8/3026F-ZTAT Version] ............................................ 461
17.1 Overview ............................................................................................................................ 461
17.2 Features .............................................................................................................................. 462
17.2.1 Block Diagram ...................................................................................................... 463
17.2.2 Pin Configuration .................................................................................................. 464
17.2.3 Register Configuration .......................................................................................... 464
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