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73M2910L

Microcontroller

TDK Corporation 

73M2910L

Microcontroller

HDLC INTERRUPT ENABLE REGISTER (HIE) SFR ADDRESS 0C4h (continued)

BIT 0 Flag Detect Interrupt Enable

When bit 0 is set, a HDLC interrupt will be generated if bit 0 (FLAG DETECT) of the HDLC Status (HSTAT)

Register is also set. If bit 0 is reset to a 0, bit 2 (NEW STATUS) of the HDLC Interrupt (HINT) Register will not

be set as a result of a flag pattern detection and no HDLC interrupt will be generated.

HDLC INTERRUPT SOURCE REGISTER (HINT) SFR ADDRESS 0C5h

Byte Addressable

Read Only Register

Reset State 00h

BIT 7

0

BIT 6

0

BIT 5

0

BIT 4

0

BIT 3

0

BIT 2

NEW

STATUS

BIT 1

RXRDY

BIT 0

TXRDY

This register is used to determine the source of HDLC interrupts. If one or more of these register bits are set,

the corresponding HDLC interrupt will go active if bit 0 of the HDLC Control 1 (HDLC1) Register is set to a 1.

BIT 2 New Status

When bit 2 is set, an unmasked HDLC status bit from the HDLC Status (HSTAT) Register is set.

Bit 2 will by cleared upon a reset and is cleared by a read of the HDLC Status Register.

BIT 1 RX Ready

When bit 1 is set, a new received byte has been loaded into the RX Data (RXD) Register. Note, received bits

that are flag, abort, or idle patterns are not considered data, and will not be loaded into the RX Data Register.

All inserted 0s have been removed from this byte. The RX Data Register must be read prior to the completed

reception of the next data byte.

Bit 1 will by cleared upon a reset and is cleared by a read of the RX Data Register.

BIT 0 TX Ready

Bit 0 is set if any HDLC TX control (HTXC) bits 3:0 are set as the first bit of data, flag or an idle byte is being

transmitted. While transmitting the current byte, the HDLC state machines are ready for commands pertaining

to the next byte to be transmitted. A new data byte must be loaded into the TX Data (TXD) Register to clear the

TX ready status bit.

Bit 0 will by cleared upon a reset and is cleared by writing to the TX Data Register.

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