CY2210PVC-4 Просмотр технического описания (PDF) - SpectraLinear Inc
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CY2210PVC-4
SpectraLinear Inc
CY2210PVC-4 Datasheet PDF : 10 Pages
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CY2210
Switching Characteristics[4, 5] Over the Operating Range
Parameter
t1
t2
Output
All
CPU, CPU/2,
APIC
Description
Output Duty Cycle[6]
Rising Edge Rate
Test Conditions
t1A/t1B
Between 0.4V and 2.0V
t2
USB, REF
Rising Edge Rate
Between 0.4V and 2.4V
t2
PCI, AGP
Rising Edge Rate
Between 0.4V and 2.4V
t3
CPU, CPU/2, Falling Edge Rate
Between 2.0V and 0.4V
APIC
t3
USB, REF
Falling Edge Rate
Between 2.4V and 0.4V
t3
PCI, AGP
Falling Edge Rate
Between 2.4V and 0.4V
t6
CPU
CPU-CPU Skew
Measured at 1.25V
t7
CPU/2
CPU/2-CPU/2 Skew
Measured at 1.25V
t8
APIC
APIC-APIC Skew
Measured at 1.25V
t9
AGP
AGP-AGP Skew
Measured at 1.5V
t10
PCI
PCI-PCI Skew
Measured at 1.5V
t11
CPU, AGP
CPU-AGP Clock Skew
CPU leads. Measured at 1.25V for
2.5V clocks and 1.5V for 3.3V clocks
t12
AGP, PCI
AGP-PCI Clock Skew
AGP leads. Measured at 1.5V
t13
CPU, APIC
CPU-APIC Clock Skew
CPU leads. Measured at 1.25V
t14
CPU, PCI
CPU-PCI Clock Skew
CPU leads. Measured at 1.25V clocks
and 1.5V for 3.3V clocks
CPU
Cycle-Cycle Clock Jitter With all outputs running (CY2210-2)
CPU
Cycle-Cycle Clock Jitter
With all outputs running
(CY2210-3/-4)
CPU
Cycle-Cycle Clock Jitter
With the USB output turned off
(CY2210-3/-4)
CPU/2
Cycle-Cycle Clock Jitter
APIC
Cycle-Cycle Clock Jitter
USB
Cycle-Cycle Clock Jitter
AGP
Cycle-Cycle Clock Jitter
REF
Cycle-Cycle Clock Jitter
CPU, PCI
Settle Time
CPU and PCI clock stabilization from
power-up
Notes:
5. All parameters specified with loaded outputs.
6. Duty cycle is measured at 1.5V when VDD = 3.3V. When VDD = 2.5V, duty cycle is measured at 1.25V.
Min.
45
1.0
0.5
1.0
1.0
0.5
1.0
0
1.5
1.5
1.5
Max.
55
4.0
2.0
4.0
4.0
2.0
4.0
175
175
250
250
500
1.5
4.0
4
4
150
250
200
250
500
500
500
1000
3
Unit
%
V/ns
V/ns
V/ns
V/ns
V/ns
V/ns
ps
ps
ps
ps
ps
ns
ns
ns
ns
ps
ps
ps
ps
ps
ps
ps
ps
ms
Rev 1.0, November 25, 2006
Page 5 of 10
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