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ISL97649BIRTZ-EVALZ

TFT-LCD Supply + DCP + VCOM Amplifier + Gate Pulse Modulator + RESET

Renesas Electronics 

ISL97649B

voltage. The rectifier diode must meet the output current and

peak inductor current requirements. Table 3 shows some

recommendations for boost converter diode.

TABLE 3. BOOST CONVERTER RECTIFIER DIODE RECOMMENDATIONS

DIODE

VR/IAVG RATING

PACKAGE

MFG

PMEG2010ER

20V/1A

SOD123W

NXP

MSS1P2U

20V/1A

MicroSMP

VISHAY

Output Capacitor

The output capacitor supplies the load directly and reduces the

ripple voltage at the output. Output ripple voltage consists of two

components (Equation 6):

1. Voltage drop due to inductor ripple current flowing through

the ESR of output capacitor.

2. Charging and discharging of output capacitor.

VRIPPLE = ILPK  ESR + -V----O---V--–---O--V----I--N--  C-----O-I--O--U----T-  -f1-s-

(EQ. 6)

For low ESR ceramic capacitors, the output ripple is dominated

by the charging and discharging of the output capacitor. The

voltage rating of the output capacitor should be greater than the

maximum output voltage.

NOTE: Capacitors have a voltage coefficient that makes their

effective capacitance drop as the voltage across them increases.

COUT in Equation 6 assumes the effective value of the capacitor

at a particular voltage and not the manufacturer’s stated value,

measured at 0V.

Table 4 shows some recommendations for output capacitors.

TABLE 4. BOOST OUTPUT CAPACITOR RECOMMENDATIONS

CAPACITOR SIZE

MFG

PART NUMBER

10µF/25V

1210

TDK

C3225X7R1E106M

10µF/25V 1210 Murata

GRM32DR61E106K

Compensation

The boost converter of ISL97649B can be compensated by an RC

network connected from the COMP pin to ground. A 15nF and

5.5k RC network is used in the ISL97649BIRTZ-EVALZ evaluation

board. The larger-value resistor and lower-value capacitor can

lower the transient overshoot, but at the expense of loop stability.

Supply Monitor Circuit

The supply monitor circuit monitors the voltage on VDIV and sets

the open-drain output RESET low when VDIV is below 1.28V

(rising) or 1.22V (falling).

There is a delay on the rising edge, controlled by a capacitor on

CD2. When VDIV exceeds 1.28V (rising), CD2 is charged up from

0V to 1.217V by a 10µA current source. When CD2 exceeds

1.217V, RESET goes tri-state. When VDIV falls below 1.22V,

RESET becomes low, with a 650 pull-down resistance. Delay

time is controlled, as shown in Equation 7:

tdelay = 121.7k  CD2

(EQ. 7)

FN7927 Rev 2.00

June 27, 2013

For example, delay time is 12.17ms if CD2 = 100nF.

Figure 11 shows the supply monitor circuit timing diagram.

VDIV

CD2

1.217V

1.28V

1.22V

RESET

RESET DELAY TIME IS

CONTROLLED BY CD2

CAPACITOR

FIGURE 11. SUPPLY MONITOR CIRCUIT TIMING DIAGRAM

Gate Pulse Modulator Circuit

The gate pulse modulator circuit functions as a three-way

multiplexer, switching VGHM between ground, GPM_LO, and VGH.

Voltage selection is provided by digital inputs VDPM (enable) and

VFLK (control). High-to-low delay and slew control are provided by

external components on pins CE and RE, respectively.

When VDPM is LOW, the block is disabled, and VGHM is

grounded. When the input voltage exceeds UVLO threshold,

VDPM starts to drive an external capacitor. When VDPM exceeds

1.215V, the GPM circuit is enabled, and the output VGHM is

determined by VFLK, RESET signal, and VGH voltage. If RESET

signal is high and VFLK is high, VGHM is pulled to VGH. When

VFLK goes low, there is a delay controlled by capacitor CE,

following which VGHM is driven to GPM_LO, with a slew rate

controlled by resistor RE. Note that GPM_LO is used only as a

reference voltage for an amplifier, and thus does not have to

source or sink a significant DC current.

Low-to-high transition is determined primarily by the switch

resistance and the external capacitive load. High-to-low transition

is more complex. Consider a case in which the block is already

enabled (VDPM is H). When VFLK is H, if CE is not externally

pulled above threshold voltage 1, Pin CE is pulled low. On the

falling edge of VFLK, a current is passed into Pin CE to charge the

external capacitor up to threshold voltage 2, providing a delay

that is adjustable by varying the capacitor on CE. Once this

threshold is reached, the output starts to be pulled down from

VGH to GPM_LO. The maximum slew current is equal to

500/(RE + 40k), and the dv/dt slew rate is Isl/CLOAD, where

CLOAD is the load capacitance applied to VGHM. The slew rate

reduces as VGHM approaches GPM_LO.

If CE is always pulled up to a voltage above threshold 1, zero

delay mode is selected; thus, there will be no delay from FLK

falling to the point where VGHM starts to fall. Slew down currents

will be identical to the previous case.

At power-down, when VIN falls to UVLO, VGHM is tied to VGH until

the VGH voltage falls to 3V. Once the VGH voltage falls below 3V,

VGHM is not actively driven until VIN is driven. Figure 12 shows

the VGHM voltage based on VIN, VGH, and RESET.

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