ISL9008AIRUBZ-T Просмотр технического описания (PDF) - Renesas Electronics

Номер в каталоге

Компоненты Описание

производитель

ISL9008AIRUBZ-T

Low Noise LDO with Low IQ, High PSRR

Renesas Electronics 

ISL9008A

Functional Description

The ISL9008A contains all circuitry required to implement a

high performance LDO. High performance is achieved through

a circuit that delivers fast transient response to varying load

conditions. In a quiescent condition, the ISL9008A adjusts its

biasing to achieve the lowest standby current consumption.

The device also integrates current limit protection, smart

thermal shutdown protection, and soft-start. Smart Thermal

shutdown protects the device against overheating. Soft-start

minimizes start-up input current surges without causing

excessive device turn-on time.

Power Control

The ISL9008A has an enable pin, EN, to control power to the

LDO output. When EN is low, the device is in shutdown mode.

In this condition, all on-chip circuits are off, and the device

draws minimum current, typically less than 0.3µA. When the

EN pin goes high, the device first polls the output of the UVLO

detector to ensure that the VIN voltage is at least 2.1V (typical).

Once verified, the device initiates a start-up sequence. During

the start-up sequence, trim settings are first read and latched.

Then sequentially, the bandgap, reference voltage and current

generation circuitry turn on. Once the references are stable,

the LDO powers up.

During operation, whenever the VIN voltage drops below about

1.84V, the ISL9008A immediately disables the LDO output.

When VIN rises back above 2.1V (assuming the EN pin is

high), the device reinitiates its start-up sequence and LDO

operation resumes automatically.

Reference Generation

The reference generation circuitry includes a trimmed

bandgap, a trimmed voltage reference divider, a trimmed

current reference generator, and an RC noise filter.

The bandgap generates a zero temperature coefficient (TC)

voltage for the regulator reference and other voltage

references required for current generation and

over-temperature detection.

A current generator provides references required for adaptive

biasing as well as references for LDO output current limit and

thermal shutdown determination.

LDO Regulation and Programmable Output Divider

The LDO Regulator is implemented with a high-gain

operational amplifier driving a PMOS pass transistor. The

design of the ISL9008A provides a regulator that has low

quiescent current, fast transient response, and overall stability

across all operating and load current conditions. LDO stability

is guaranteed for a 1µF to 4.7µF output capacitor that has a

tolerance better than 20% and ESR less than 200mW. The

design is performance-optimized for a 1µF capacitor. Unless

limited by the application, use of an output capacitor value

above 4.7µF is not recommended as LDO performance

improvement is minimal.

Soft-start circuitry integrated into each LDO limits the initial

ramp-up rate to about 30µs/V to minimize current surge. The

ISL9008A provides short-circuit protection by limiting the

output current to about 265mA (typ).

The LDO uses an independently trimmed 1V reference as its

input. An internal resistor divider drops the LDO output voltage

down to 1V. This is compared to the 1V reference for

regulation. The resistor division ratio is programmed in the

factory.

Overheat Detection

The bandgap outputs a proportional-to-temperature current

that is indicative of the temperature of the silicon. This current

is compared with references to determine if the device is in

danger of damage due to overheating. When the die

temperature reaches about +140°C, the LDO momentarily

shuts down until the die cools sufficiently. In the overheat

condition, if the LDO sources more than 50mA it will be shut

off. Once the die temperature falls back below about +110°C,

the disabled LDO is re-enabled and soft-start automatically

takes place.

Exposed Thermal Pad

The ISL9008A with µTDFN package has an exposed thermal

pad at the bottom side of the package. The PCB layout should

connect the exposed pad to some copper on the component

layer for a good thermal conductivity. Since the copper area on

the component layer is limited by the surrounding pins of the

package, it is more effective to use some thermal vias to

conduct the heat to other copper layers if possible.

Electrically, the copper and vias connecting to the exposed pad

should be isolated from any other pin connection, they are

strictly for thermal enhancement purpose.

FN6300 Rev 5.00

June 27, 2014

Page 9 of 12

Share Link: