ISL6532B Просмотр технического описания (PDF) - Renesas Electronics

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ISL6532B

ACPI Regulator/Controller for Dual Channel DDR Memory Systems

Renesas Electronics 

ISL6532B

S3

S5

12VATX 2V/DIV

VDDQ

500mV/DIV

VTT

500mV/DIV

PGOOD

5V/DIV

12V POR

2048 CLOCK

CYCLES

PGOOD COMPARATOR

ENABLED

FIGURE 2. TYPICAL S3 TO S0 STATE TRANSITION

overcurrent event on the VTT LDO, only the VTT LDO is

disabled. Once the over current condition on the VTT rail is

removed, VTT will recover.

Over/Under Voltage Protection.

Both the internal VTT LDO and the VDDQ regulator are

protected from faults through internal Over/Under voltage

detection circuitry. If either rail falls below 85% of the targeted

voltage, then an undervoltage event is tripped. An under voltage

will disable all regulators for a period of 3 soft-start cycles, after

which a normal soft-start is initiated. If the output remains under

85% of target, the regulators will continue to be disabled and

soft-started in a hiccup mode until the fault is cleared. See

Figure 3.

If either rail exceeds 115% of the targeted voltage, then all

outputs are immediately disabled. The ISL6532B will not re-

enable the outputs until either the bias voltage is toggled in

order to initiate a POR or the SLP_S5 signal is forced LOW

and then back to HIGH.

Thermal Protection (S0/S3 State)

If the ISL6532B IC junction temperature reaches a nominal

temperature of 140oC, all regulators will be disabled. The

ISL6532B will not re-enable the outputs until the junction

temperature drops below 110oC and either the bias voltage is

toggled in order to initiate a POR or the SLP_S5 signal is

forced LOW and then back to HIGH.

Shoot-Through Protection

A shoot-through condition occurs when both the upper and

lower MOSFETs are turned on simultaneously, effectively

shorting the input voltage to ground. To protect from a shoot-

through condition, the ISL6532B incorporates specialized

circuitry which insures that complementary MOSFETs are not

ON simultaneously.

VDDQ

VTT

500mV/DIV

INTERNAL DELAY

DELAY INTERVAL

T0

T1

T2

TIME

FIGURE 3. VTT/VDDQ LDO UNDER VOLTAGE PROTECTION

RESPONSES

The adaptive shoot-through protection utilized by the VDDQ

regulator looks at the lower gate drive pin, LGATE, and the

upper gate drive pin, UGATE, to determine whether a

MOSFET is ON or OFF. If the voltage from UGATE or from

LGATE to GND is less than 0.8V, then the respective MOSFET

is defined as being OFF and the other MOSFET is allowed to

be turned ON. This method allows the VDDQ regulator to both

source and sink current.

Since the voltage of the MOSFET gates are being measured to

determine the state of the MOSFET, the designer is

encouraged to consider the repercussions of introducing

external components between the gate drivers and their

respective MOSFET gates before actually implementing such

measures. Doing so may interfere with the shoot-through

protection.

Application Guidelines

Layout Considerations

Layout is very important in high frequency switching converter

design. With power devices switching efficiently at 250kHz, the

resulting current transitions from one device to another cause

voltage spikes across the interconnecting impedances and

parasitic circuit elements. These voltage spikes can degrade

efficiency, radiate noise into the circuit, and lead to device

over-voltage stress. Careful component layout and printed

circuit board design minimizes these voltage spikes.

As an example, consider the turn-off transition of the upper

MOSFET. Prior to turn-off, the MOSFET is carrying the full

load current. During turn-off, current stops flowing in the

MOSFET and is picked up by the lower MOSFET. Any

FN9120 Rev 3.00

Jul 2004

Page 9 of 15

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