ISL51002 Просмотр технического описания (PDF) - Renesas Electronics
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ISL51002
Renesas Electronics
ISL51002 Datasheet PDF : 33 Pages
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ISL51002
Timing Diagrams
Data Output Setup and Hold Timing
DATACLK
DATACLK
PIXEL DATA
tSETUP
tHOLD
RGB Output Data Timing and Latency
HSYNCIN
THE HSYNC EDGE (PROGRAMMABLE LEADING OR TRAILING) THAT THE DPLL IS LOCKED
TO. THE SAMPLING PHASE SETTING DETERMINES ITS RELATIVE POSITION TO THE REST
OF THE AFE’S OUTPUT SIGNALS
ANALOG
VIDEO IN
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
DATACLK
R/G/B[9:0]
8 DATACLK PIPELINE LATENCY
D0
D1
D2
D3
HSOUT
PROGRAMMABLE
WIDTH AND POLARITY
YUV Output Data Timing and Latency
HSYNCIN
THE HSYNC EDGE (PROGRAMMABLE LEADING OR TRAILING) THAT THE DPLL IS LOCKED TO.
THE SAMPLING PHASE SETTING DETERMINES ITS RELATIVE POSITION TO THE REST OF THE
AFE’S OUTPUT SIGNALS
ANALOG
VIDEO IN
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
DATACLK
G[9:0]
8 DATACLK PIPELINE LATENCY
G0 (YO) G1 (Y1) G2 (Y2) G3 (Y3)
R[9:0]
B0 (UO) R0 (V0) B2 (U2) R2 (V2)
B[9:0]
HSOUT
PROGRAMMABLE
WIDTH AND POLARITY
FN6164 Rev 3.00
February 29, 2012
Page 7 of 33
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