2671286IBZ Просмотр технического описания (PDF) - Renesas Electronics
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2671286IBZ Datasheet PDF : 15 Pages
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ISL2671286
Timing Specifications At fCLK = 200kHz , unless otherwise noted. Typical values are at TA = +25°C. Boldface limits apply over the
operating temperature range, -40°C to +85°C. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
MAX
(Note 8) TYP (Note 8) UNITS
thDO
Output Data Remains Valid After DCLOCK CLOAD = 100pF
15
30
ns
tf
DOUT Fall Time
See test circuits; Figure 4
1
100
ns
tR
DOUT Rise Time
See test circuits; Figure 4
1
100
ns
tCSD
Delay Time, CS/SHDN to DCLOCK
See operating sequence; Figure 3
0
ns
tSUCS
Delay Time, CS/SHDN to DCLOCK
See operating sequence; Figure 3
30
ns
NOTE:
11. During characterization, tDIS is measured from the release point with a 10pF load (see Figure 4) and the equivalent timing using the ADS1286
loading (3kΩ, 100pF) is calculated.
CS/SHDN
DCLOCK
DOUT
CS/SHDN
DCLOCK
DOUT
tSUCS
tCYC
POWER
DOWN
tCSD
Hi-Z
tSMPL
Null
Bit B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0(1)
Hi-Z
(MSB)
tCONV
tDATA
Note: (1) After completing the data transfer, additional clocks applied while CS/SHDN is low
will result in the previous data being retransmitted LSB-first, followed by indefinite
transmission of zeros
tCYC
Null
Bit B11 B10 B9 B8
tSUCS
POWER
DOWN
tCSD
Hi-Z
tSMPL
Null
Bit B11 B10 B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9 B10 B11
Hi-Z
(2)
(MSB)
tCONV
tDATA
Note: (2) After completing the data transfer, additional clocks applied while CS/SHDN is low
will result in indefinite transmission of zeros
FIGURE 3. SERIAL INTERFACE TIMING DIAGRAM
+VCC
RL
2.85k
OUTPUT PIN
CL
10pF
FIGURE 4. EQUIVALENT LOAD CIRCUIT
FN7863 Rev 0.00
November 1, 2011
Page 5 of 15
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