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ML9092-03TB Просмотр технического описания (PDF) - LAPIS Semiconductor Co., Ltd.

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ML9092-03TB
LAPIS
LAPIS Semiconductor Co., Ltd. LAPIS
ML9092-03TB Datasheet PDF : 66 Pages
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LAPIS Semiconductor
FEDL9092-01
ML9092-01/02/03/04
ML9092-03
Function
CPU interface
Oscillation
Pin
Symbol
Type
63
CS
I
64
CP
I
65
DI/O
I/O
66
KREQ
O
77
OSC1
I
78
OSC2
O
Control signal
67
RESET
I
79
TEST
I
62–59
C0–C3
I
Switch signal
58–53
R0–R5
O
51, 52
A, B
I
Port output
80
PA0
O
LCD driver output
50–1,
SEG1–SEG60
O
100–91
90–81
COM1–COM10
O
76
VDD
68
VSS
Power supply
74
VHIN
73, 72, 70, 69 V0, V1, V2, V3
75, 71
NC
Description
Chip select signal input pin
Shift clock signal input pin. This pin is
connected to the Schmitt circuit internally.
Serial data signal I/O pin. This pin is
connected to the Schmitt circuit internally.
Key scan read and rotary encoder read
READY signal output pin.
Connect external resistors with this pin.
This pin is connected to the Schmitt circuit
internally.
If using an external clock, input it from the
OSC1 pin and leave the OSC2 pin open.
Reset input. Initial settings can be
established by applying a “L” level to this
pin. This pin is connected to the Schmitt
circuit internally.
Test input pin. This pin is connected to the
VSS pin.
Input pins that detect status of key
switches. These pins are connected to the
Schmitt circuit internally.
Key switch scan signal output pins
Rotary encoder signal input pins.
These pins are connected to the Schmitt
circuit internally.
Port A output pin
LCD segment driver output pins
LCD common driver output pins
Logic power supply pin
GND pin
High-voltage power supply pin
LCD bias pins
Should be left open.
13/66

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