ML7033GA Просмотр технического описания (PDF) - LAPIS Semiconductor Co., Ltd.
Номер в каталоге
Компоненты Описание
Список матч
ML7033GA Datasheet PDF : 52 Pages
| |||
FEDL7033-04
ML7033
TIMING DIAGRAM
Transmit Timing - 8-bit PCM Mode with LIN (CR0-B3) bit = “0”
Long Frame Sync Mode with SHORT (CR0-B4) bit = “0”
MCK
BCLK
XSYNC
PCMOUT
PCMOSY
1
tXS
tXD1
tXD3
2
tSX
tW S
tSD
MSD
tMB
3
D2
D3
4
tXD2
D4
5
D5
6
D6
7
D7
8
D8
tXD4
Short Frame Sync Mode with SHORT (CR0-B4) bit = “1”
MCK
BCLK
XSYNC
PCMOUT
PCMOSY
tMB
1
2
3
4
5
6
7
8
tSX
tXS
tW S
tXD1
tXD2
MSD
D2
D3
D4
D5
D6
D7
tXD3
D8
tXD4
Figure 1 Transmit Side Timing Diagram
Receive Timing - 8-bit PCM Mode with LIN (CR0-B3) bit = “0”
Long Frame Sync Mode with SHORT (CR0-B4) bit = “0”
MCK
BCLK
tRS
RSYNC
P C M IN
tMB
1
2
3
tSR
tW S
tDS
MSD
D2
D3
4
tDH
D4
5
D5
6
D6
7
D7
8
D8
Short Frame Sync Mode with SHORT (CR0-B4) bit = “1”
MCK
BCLK
RSYNC
P C M IN
tMB
1
2
3
4
tSR
tRS
tW S
tDS
tDH
MSD
D2
D3
5
D4
6
D5
7
D6
8
D7
Figure 2 Receive Side Timing Diagram
Note: The above timings are also valid in 14-bit linear PCM Mode with the LIN (CR0-B3) bit = “1”,
except that the number of data bits on the PCMIN and PCMOUT signals changes from 8 to 14.
13/52
Share Link: 