Philips Semiconductors
Inverter
Product specification
74AHC3G04; 74AHCT3G04
FEATURES
• Symmetrical output impedance
• High noise immunity
• ESD protection:
– HBM EIA/JESD22-A114-A exceeds 2000 V
– MM EIA/JESD22-A115-A exceeds 200 V
– CDM EIA/JESD22-C101 exceeds 1000 V.
• Low power dissipation
• Balanced propagation delays
• SOT505-2 and SOT765-1 package
• Specified from −40 to +85 °C and −40 to +125 °C.
DESCRIPTION
The 74AHC3G04/74AHCT3G04 are high-speed Si-gate
CMOS devices.
The 74AHC3G04/74AHCT3G04 provides three inverting
buffer.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 3.0 ns.
SYMBOL
PARAMETER
CONDITIONS
tPHL/tPLH
CI
CPD
propagation delay input A to output Y CL = 15 pF; VCC = 5 V
input capacitance
power dissipation capacitance
CL = 50 pF; f = 1 MHz;
notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
∑(CL × VCC2 × fo) = sum of outputs.
2. The condition is VI = GND to VCC.
TYPICAL
UNIT
74AHC3G04 74AHCT3G04
3.1
3.4
ns
1.5
1.5
pF
9
10
pF
FUNCTION TABLE
See note 1.
INPUT
nA
L
H
Note
1. H = HIGH voltage level;
L = LOW voltage level.
OUTPUT
nY
H
L
2003 Nov 06
2