74ALVC32D Просмотр технического описания (PDF) - NXP Semiconductors.

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74ALVC32D

Quad 2-input OR gate

NXP Semiconductors. 

NXP Semiconductors

4. Functional diagram

1 1A

2 1B

4 2A

5 2B

9 3A

10 3B

12 4A

13 4B

Fig 1. Logic symbol

1Y 3

2Y 6

3Y 8

4Y 11

mna242

A

B

Fig 3. Logic diagram (one gate)

5. Pinning information

5.1 Pinning

1A 1

1B 2

1Y 3

2A 4

2B 5

2Y 6

GND 7

14 VCC

13 4B

12 4A

32

11 4Y

10 3B

9 3A

8 3Y

001aad101

Fig 4. Pin configuration SO14 and TSSOP14

74ALVC32

Quad 2-input OR gate

1

≥1

3

2

4

≥1

6

5

9

≥1

8

10

12

≥1

11

13

mna243

Fig 2. IEC logic symbol

Y

mna241

terminal 1

index area

1B 2

1Y 3

2A 4

2B 5

2Y 6

32

GND(1)

13 4B

12 4A

11 4Y

10 3B

9 3A

001aad102

Transparent top view

(1) The die substrate is attached to this pad using

conductive die attach material. It can not be used as

a supply pin or input.

Fig 5. Pin configuration DHVQFN14

74ALVC32_2

Product data sheet

Rev. 02 — 10 December 2007

© NXP B.V. 2007. All rights reserved.

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