SM5904BF Просмотр технического описания (PDF) - Nippon Precision Circuits

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Компоненты Описание

производитель

SM5904BF

compression and non compression type shock-proof memory controller

Nippon Precision Circuits  

Pin description

SM5904BF

Pin number

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

Pin name

VDD2

UC1

UC2

UC3

UC4

VSS2

DIT

NTEST1

CLK

VSS1

YSRDATA

YLRCK

YSCK

ZSCK

ZLRCK

ZSRDATA

YFLAG

YFCLK

YBLKCK

NRESET

ZSENSE

VDD1

YDMUTE

YMLD

YMDATA

YMCLK

NTEST2

NCAS2

D2

D3

D0

D1

NWE

NRAS

A9

A8

A7

A6

A5

A4

A0

A1

A2

A3

I/O

-

Ip/O

Ip/O

Ip/O

Ip/O

-

O

Ip

I

-

I

I

I

O

O

O

I

I

I

I

O

-

I

I

I

I

Ip

O

Ip/O

Ip/O

Ip/O

Ip/O

O

O

O

O

O

O

O

O

O

O

O

O

Function

VDD supply pin

Microcontroller interface extension I/O 1

Microcontroller interface extension I/O 2

Microcontroller interface extension I/O 3

Microcontroller interface extension I/O 4

Ground

Digital audio interface

Test pin

16.9344 MHz clock input

Ground

Audio serial input data

Audio serial input LR clock

Audio serial input bit clock

Audio serial output bit clock

Audio serial output LR clock

Audio serial output data

Signal processor IC RAM overflow flag

Crystal-controlled frame clock

Subcode block clock signal

System reset pin

Microcontroller interface status output

VDD supply pin

Forced mute pin

Microcontroller interface latch clock

Microcontroller interface serial data

Microcontroller interface shift clock

Test pin

DRAM2 CAS control(Use External DRAM)

DRAM data input/output 2

DRAM data input/output 3

DRAM data input/output 0

DRAM data input/output 1

DRAM WE control

DRAM RAS control

DRAM address 9

DRAM address 8

DRAM address 7

DRAM address 6

DRAM address 5

DRAM address 4

DRAM address 0

DRAM address 1

DRAM address 2

DRAM address 3

Setting

H

L

Test

Left channel Right channel

Left channel Right channel

Overflow

Reset

Mute

Test

Ip : Input pin with pull-up resistor Ip/O : Input/Output pin (With pull-up resistor when in input mode)

28, 33 to 44 pins for high-impedance output and 29 to 32 pins for input pull-up condition except for using external DRAM.

NIPPON PRECISION CIRCUITS-3

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