11. Output Clock Duty Cycle (tDCC, tDCR = tb/ta)
ta
tb
CKOUT,
REFOUT
12. Input Frequency (fin = 1/tin)
tin
XIN
13. Output Slew Rate (SR)
MB88154A
1.5 V
0.8 VDD
CKOUT,
REFOUT
tr
Note : SR = (2.4−0.4) /tr, SR = (2.4−0.4) /tf
2.4 V
0.4 V
tf
Document Number: 002-08252 Rev. *B
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