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MAX122ACAG

500ksps, 12-Bit ADCs with Track/Hold and Reference

Maxim Integrated 

MAX120/MAX122

500ksps, 12-Bit ADCs with Track/Hold

and Reference

Figure 8. Stand-Alone Mode (Mode 2)

Initialization After Power-Up

On power-up, the first MAX120/MAX122 conversion is

valid if the following conditions are met:

1) Allow 14 clock cycles for the internal T/H to enter the

track mode, plus a minimum of 350ns in the track

mode for the data-acquisition time.

2) Make sure the reference voltage has settled. Allow

0.5ms for each 1µF of reference bypass capacitance

(11ms for a 22µF capacitor).

Operating Modes

Mode 1: (Full-Control Mode)

Figure 7 shows the timing diagram for full-control mode

(mode 1). In this mode, the µP controls the conversion­

start and data-read operations independently.

A falling edge on CONVST places the T/H into hold mode

and starts a conversion in the SAR. The conversion is

complete in 13 or 14 clock cycles as discussed in the

Clock and Control Synchronization section. A change in

the INT/BUSY output state signals the end of a conver-

sion as follows:

If MODE = VDD, the end of conversion is signaled by the

INT/BUSY output falling edge.

If MODE = OPEN or DGND, the INT/BUSY output goes

low while the conversion is in progress and returns high

when the conversion is complete.

Figure 9. Slow-Memory Mode (Mode 3)

When the conversion is complete, the data can be read

without initiating a new conversion by pulling RD and CS

low and leaving CONVST high. To start a new conversion

without reading data, RD and CS should remain high

while CONVST is driven low. To simultaneous read data

and initiate a new conversion, CONVST, RD, and CS

should all be pulled low. Note: Allow at least 350ns for

T/H acquisition time between the end of one conversion

and the beginning of the next.

Mode 2: Stand-Alone Operation

(MODE= OPEN, RD = CS = DGND)

For systems that do not use or require full-bus interfac-

ing, the MAX120/MAX122 can be operated in stand-alone

mode directly linked to memory through DMA ports or a

FIFO buffer. In stand-alone mode, a conversion is initi-

ated by a falling edge on CONVST. The data outputs are

always enabled; data changes at the end of a conversion

as indicated by a rising edge on INT/BUSY. See Figure 8

for stand-alone mode timing.

Mode 3: Slow-Memory Mode

(CONVST = GND, MODE= OPEN)

Taking RD and CS lo laces the T/H into hold mode and

starts a conversion. INT/BUSY remains low while the

conversion is in progress and can be used as a wait input

to the µP. Data from the previous conversion appears on

the data bus until the conversion end is indicated by INT/

BUSY. See Figure 9 for slow-memory mode timing.

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