ML4819 Просмотр технического описания (PDF) - Fairchild Semiconductor
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ML4819 Datasheet PDF : 15 Pages
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SLOPE COMPENSATION
Slope compensation is accomplished by adding 1/2 of the
current flowing out of pin 12 to pin 1 (for the PFC section
and pin 9 (for the PWM section). The amount of slope
compensation is equal to (IRAMP COMP/2) × RL where RL is
the impedance to GND on pin 1 or pin 9. Since most of
the PWM applications will be limited to 50% duty cycle,
slope compensation should not be needed for the PWM
section. This can be defeated by using a low impedance
load to the current sense on pin 9.
RT
10
CT
20
OSC
VREF
IR(SC)
9V
IR(SC) Ϭ 2
RAMP COMP
12
RSC
Q1
IR(SC) Ϭ 2
SLOPE
COMPENSATION
TO PIN 9
TO PIN 1
Figure 7. Slope Compensation Circuit
500
400
300
200
100
0
0
4.5V
4.0V
3.5V
3.0V
100
200
300
400
SINE INPUT CURRENT (µA)
2.5V
2.0V
1. 5V
500
Figure 8. Gain Modulator Linearity
UNDER VOLTAGE LOCKOUT
On power-up the ML4819 remains in the UVLO condition;
output low and quiescent current low. The IC becomes
operational when VCC reaches 16V. When VCC drops
below 10V, the UVLO condition is imposed. During the
UVLO condition, the 5V VREF pin is “off”, making it
usable as a status flag.
ML4819
ENABLE
VREF
VREF
GEN.
9V
–
INTERNAL
BIAS
+
5V VREF
VCC
Figure 9. Under-Voltage Lockout Block Diagram
40
30
20
10
TA = 25 C
0
0
10
20
30
40
VCC, SUPPLY VOLTAGE (V)
Figure 10a. Total Supply Current vs. Supply Voltage
35
30
25
OPERATING
CURRENT
20
15
10
5
START-UP
0
0 10 20 30 40 50 60 70
TEMPERATURE ( C)
Figure 10b. Supply Current (ICC) vs. Temperature
REV. 1.0 10/10/2000
7
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