MCM67J518FN6 Просмотр технического описания (PDF) - Motorola => Freescale
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MCM67J518FN6 Datasheet PDF : 12 Pages
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K
ADSC
ADSP
A0 – A14
BLOCK DIAGRAM (See Note)
ADV
BURST LOGIC
Q0
A0
BINARY
COUNTER
Q1
CLR
A1
INTERNAL
A0′ ADDRESS
15
A1′
32K x 18
MEMORY
ARRAY
ADDRESS
REGISTER
2
A1 – A0
A2 – A14
15
18
99
WRITE
UW
REGISTER
LW
DATA–IN
REGISTERS
E
G
9
DQ0 – DQ8
9
DQ9 – DQ17
ENABLE
REGISTER
9
9
DATA–OUT
REGISTERS
OUTPUT
BUFFER
NOTE: All registers are positive–edge triggered. The ADSC or ADSP signals control the duration of the burst and the start of the
next burst. When ADSP is sampled low, any ongoing burst is interrupted and a read (independent of W and ADSC) is per-
formed using the new external address. Alternatively, an ADSP–initiated two cycle WRITE can be performed by negating
both ADSP and ADSC and asserting LW and/or UW with valid data on the second cycle (see Single Write cycle in WRITE
CYCLES timing diagram). When ADSC is sampled low (and ADSP is sampled high), any ongoing burst is interrupted and
a read or write (dependent on W) is performed using the new external address. Chip enable (E) is sampled only when a
new base address is loaded. After the first cycle of the burst, ADV controls subsequent burst cycles. When ADV is sampled
low, the internal address is advanced prior to the operation. When ADV is sampled high, the internal address is not ad-
vanced, thus inserting a wait state into the burst sequence accesses. Upon completion of a burst, the address will wrap
around to its initial state. See BURST SEQUENCE TABLE. Write refers to either or both byte write enables (LW, UW).
BURST SEQUENCE TABLE (See Note)
External Address A14 – A2
A1
A0
1st Burst Address A14 – A2
A1
A0
2nd Burst Address A14 – A2
A1
A0
3rd Burst Address A14 – A2
A1
A0
NOTE: The burst wraps around to its initial state upon completion.
MCM67J518
2
MOTOROLA FAST SRAM
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