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MAX192ACAP

Low-Power, 8-Channel,Serial 10-Bit ADC

Maxim Integrated 

Low-Power, 8-Channel,

Serial 10-Bit ADC

Table 5. Worst-Case Power-Up Delay Times

Reference

Buffer

Enabled

Enabled

Enabled

Enabled

Disabled

Disabled

Reference-

Buffer

Compensation

Mode

Internal

Internal

External

External

VREF

Capacitor

(µF)

4.7

4.7

Power-

Down

Mode

Fast

Full

Fast

Full

Fast

Full

Power-Up

Delay

(sec)

5µ

300µ

See Figure 14c

See Figure 14c

2µ

2µ

Maximum

Sampling

Rate (ksps)

26

26

133

133

133

133

Table 6. Software Shutdown and Clock

Mode

PD1 PD0 Device Mode

1

1

External Clock Mode

1

0

Internal Clock Mode

0

1

Fast Power-Down Mode

0

0

Full Power-Down Mode

tors that will not discharge more than 1/2LSB while shut

down. In shutdown, the capacitor has to supply the cur-

rent into the reference (1.5µA typ) and the transient cur-

rents at power-up.

Figures 12a and 12b illustrate the various power-down

sequences in both external and internal clock modes.

Software Power-Down

Software power-down is activated using bits PD1 and

PD0 of the control byte. As shown in Table 6, PD1 and

PD0 also specify the clock mode. When software shut-

down is asserted, the ADC will continue to operate in

the last specified clock mode until the conversion is

complete. Then the ADC powers down into a low quies-

cent-current state. In internal clock mode, the interface

remains active and conversion results may be clocked

out while the MAX192 has already entered a software

power-down.

The first logical 1 on DIN will be interpreted as a start

bit, and powers up the MAX192. Following the start bit,

the data input word or control byte also determines

clock and power-down modes. For example, if the DIN

word contains PD1 = 1, then the chip will remain pow-

ered up. If PD1 = 0, a power-down will resume after

one conversion.

Table 7. Hard-Wired Shutdown and

Compensation Mode

SHDN

State

Device

Mode

Reference-Buffer

Compensation

1

Floating

0

Enabled

Internal Compensation

Enabled

External Compensation

Full Power-Down N/A

Hardware Power-Down

The SHDN pin places the converter into the full

power-down mode. Unlike with the software shutdown

modes, conversion is not completed. It stops coinci-

dentally with SHDN being brought low. There is no

power-up delay if an external reference is used and is

not shut down. The SHDN pin also selects internal or

external reference compensation (see Table 7).

Power-Down Sequencing

The MAX192 auto power-down modes can save con-

siderable power when operating at less than maximum

sample rates. The following discussion illustrates the

various power-down sequences.

Lowest Power at up to 500

Conversions/Channel/Second

The following examples illustrate two different

power-down sequences. Other combinations of clock

rates, compensation modes, and power-down modes

may give lowest power consumption in other applica-

tions.

Figure 14a depicts the MAX192 power consumption for

one or eight channel conversions utilizing full

power-down mode and internal reference compensa-

tion. A 0.01µF bypass capacitor at REFADJ forms an

16 ______________________________________________________________________________________

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