MAX192ACAP Просмотр технического описания (PDF) - Maxim Integrated

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MAX192ACAP

Low-Power, 8-Channel,Serial 10-Bit ADC

Maxim Integrated 

Low-Power, 8-Channel,

Serial 10-Bit ADC

CS

SSTRB

•••

tSDV

•••

•••

tSTR

•••

SCLK

•• • •

PD0 CLOCKED IN

Figure 8. External Clock Mode SSTRB Detailed Timing

tSSTRB

tSSTRB

• • ••

CS

SCLK

DIN

1 2 345678

START SEL2 SEL1 SEL0

UNI/

BIP

SGL/

DIF

PD1

PD0

9 10 11 12

18 19 20 21 22 23 24

SSTRB

DOUT

A/D STATE

tCONV

ACQUISITION CONVERSION

IDLE

10µs MAX

1.5µs (CLK = 2MHz)

Figure 9. Internal Clock Mode Timing

Most microcontrollers require that conversions occur in

multiples of 8 SCLK clocks; 16 clocks per conversion

will typically be the fastest that a microcontroller can

drive the MAX192. Figure 11b shows the serial-inter-

face timing necessary to perform a conversion every 16

SCLK cycles in external clock mode.

__________ Applications Information

Power-On Reset

When power is first applied and if SHDN is not pulled

low, internal power-on reset circuitry will activate the

MAX192 in internal clock mode, ready to convert with

SSTRB = high. After the power supplies have been sta-

bilized, the internal reset time is 100µs and no conver-

sions should be performed during this phase. SSTRB is

high on power-up and, if CS is low, the first logical 1 on

DIN will be interpreted as a start bit. Until a conversion

takes place, DOUT will shift out zeros.

B9

MSB

B8

B7

IDLE

B0

LSB

S1

FILLED WITH

S0 ZEROS

Reference-Buffer Compensation

In addition to its shutdown function, the SHDN pin also

selects internal or external compensation. The compen-

sation affects both power-up time and maximum conver-

sion speed. Compensated or not, the minimum clock

rate is 100kHz due to droop on the sample-and-hold.

To select external compensation, float SHDN. See the

Typical Operating Circuit, which uses a 4.7µF capacitor

at VREF. A value of 4.7µF or greater ensures stability

and allows operation of the converter at the full clock

speed of 2MHz. External compensation increases

power-up time (see the Choosing Power-Down Mode

section, and Table 5).

Internal compensation requires no external capacitor at

VREF, and is selected by pulling SHDN high. Internal

compensation allows for shortest power-up times, but is

only available using an external clock and reduces the

maximum clock rate to 400kHz.

______________________________________________________________________________________ 13

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