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HM62W8511HC Просмотр технического описания (PDF) - Hitachi -> Renesas Electronics

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HM62W8511HC
Hitachi
Hitachi -> Renesas Electronics Hitachi
HM62W8511HC Datasheet PDF : 14 Pages
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HM62W8511HC Series
4M High Speed SRAM (512-kword × 8-bit)
ADE-203-1201 (Z)
Preliminary
Rev. 0.0
Sep. 20, 2000
Description
The HM62W8511HC is a 4-Mbit high speed static RAM organized 512-kword × 8-bit. It has realized high
speed access time by employing CMOS process (6-transistor memory cell) and high speed circuit designing
technology. It is most appropriate for the application which requires high speed, high density memory and
wide bit width configuration, such as cache and buffer memory in system. The HM62W8511HC is packaged
in 400-mil 36-pin SOJ for high density surface mounting.
Features
Single supply : 3.3 V ± 0.3 V
Access time : 10 ns (max)
Completely static memory
No clock or timing strobe required
Equal access and cycle times
Directly TTL compatible
All inputs and outputs
Operating current : 115 mA (max)
TTL standby current : 40 mA (max)
CMOS standby current : 5 mA (max)
: 1 mA (max) (L-version)
Data retension current : 0.6 mA (max) (L-version)
Data retension voltage : 2 V (min) (L-version)
Center VCC and VSS type pinout
Preliminary: The specification of this device are subject to change without notice. Please contact your nearest
Hitachi’s Sales Dept. regarding specification.

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