EBS52UC8APFA Просмотр технического описания (PDF) - Elpida Memory, Inc

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EBS52UC8APFA

512MB Unbuffered SDRAM DIMM

Elpida Memory, Inc 

EBS52UC8APFA

Pin Functions

CLK0 to CLK3 (input pin): CLK is the master clock input to this pin. The other input signals are referred at CLK

rising edge.

/CS0 to /CS3 (input pin): When /CS is Low, the command input cycle becomes valid. When /CS is High, all inputs

are ignored. However, internal operations (bank active, burst operations, etc.) are held.

/RAS, /CAS and /WE (input pins): Although these pin names are the same as those of conventional DRAMs, they

function in a different way. These pins define operation commands (read, write, etc.) depending on the combination

of their voltage levels. For details, refer to the command operation section.

A0 to A12 (input pins): Row address (AX0 to AX12) is determined by A0 to A12 level at the bank active command

cycle CLK rising edge. Column address (AY0 to AY9) is determined by A0 to A9 level at the read or write command

cycle CLK rising edge. And this column address becomes burst access start address. A10 defines the precharge

mode. When A10 = High at the precharge command cycle, all banks are precharged. But when A10 = Low at the

precharge command cycle, only the bank that is selected by BA0 and BA1 (BA) is precharged.

BA0 and BA1 (input pin)

BA0 and BA1 are bank select signal (BA). (See Bank Select Signal Table)

[Bank Select Signal Table]

BA0

BA1

Bank 0

L

L

Bank 1

H

L

Bank 2

L

H

Bank 3

H

H

Remark: H: VIH. L: VIL.

CKE0, CKE1 (input pin): This pin determines whether or not the next CLK is valid. If CKE is High, the next CLK

rising edge is valid. If CKE is Low, the next CLK rising edge is invalid. This pin is used for power-down and clock

suspend modes.

DQMB0 to DQMB7 (input pins): Read operation: If DQMB is High, the output buffer becomes High-Z. If the

DQMB is Low, the output buffer becomes Low-Z.

Write operation: If DQMB is High, the previous data is held (the new data is not written). If DQMB is Low, the data

is written.

DQ0 to DQ63 (input/output pins): Data is input to and output from these pins.

VDD (power supply pins): 3.3V is applied.

VSS (power supply pins): Ground is connected.

Detailed Operation Part

Refer to the EDS2504APTA/08APTA/16APTA datasheet (E0272E).

Data Sheet E0208E20 (Ver. 2.0)

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