74LVC257APW,118 Просмотр технического описания (PDF) - NXP Semiconductors.

Номер в каталоге

Компоненты Описание

Список матч

74LVC257APW,118

Quad 2-input multiplexer with 5 V tolerant inputs/outputs; 3-state

NXP Semiconductors. 

Nexperia

74LVC257A

Quad 2-input multiplexer with 5V tolerant; 3-state

2 1I0

3 1I1

5 2I0

6 2I1

11 3I0 SELECTOR

10 3I1

14 4I0

13 4I1

1Y 4

3-STATE

MULTI-

PLEXER

OUTPUTS

2Y 7

3Y 9

4Y 12

1S

15 OE

Fig 3. Functional diagram

mna868

5. Pinning information

5.1 Pinning

74LVC257A

S1

1I0 2

1I1 3

1Y 4

2I0 5

2I1 6

2Y 7

GND 8

16 VCC

15 OE

14 4I0

13 4I1

12 4Y

11 3I0

10 3I1

9 3Y

001aad097

Fig 5. Pin configuration for SO24 and (T)SSOP24

1I1

1I0

2I1

2I0

3I1

3I0

4I1

4I0

OE

S

Fig 4. Logic diagram

1Y

2Y

3Y

4Y

mna867

terminal 1

index area

1I0 2

1I1 3

1Y 4

2I0 5

2I1 6

2Y 7

257A

GND(1)

15 OE

14 4I0

13 4I1

12 4Y

11 3I0

10 3I1

001aad098

Transparent top view

(1) This is not a supply pin. The substrate is attached to this

pad using conductive die attach material. There is no

electrical or mechanical requirement to solder this pad.

However, if it is soldered, the solder land should remain

floating or be connected to GND.

Fig 6. Pin configuration for DHVQFN24

74LVC257A

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 6 — 28 November 2011

© Nexperia B.V. 2017. All rights reserved

3 of 18

Share Link: