CXD2467AQ Просмотр технического описания (PDF) - Sony Semiconductor

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CXD2467AQ

Digital Signal Driver/Timing Generator

Sony Semiconductor 

CXD2467AQ

Parallel Transfer Data AC Characteristics

(VDD = 3.3 ± 0.3V, VSS = 0V, Topr = –20 to +75°C)

Item

PCTL setup time with respect to rise of PCLK

Symbol Min.

tcs

8T∗5

Typ.

—

Max.

—

PCTL hold time with respect to rise of PCLK

tch

8T

—

—

PDAT[9:0] setup time with respect to rise of PCLK

tds

4T

—

—

PDAT[9:0] hold time with respect to rise of PCLK

tdh

4T

—

—

PCLK pulse width

tw

4T

—

—

∗5 T: Master clock (CLK1P/CLK1N, CLK1C, CLK3P/CLK3N, CLK3C) cycle [ns]

Timing Definition

PCTL

PCLK

PDAT[9:0]

tcs

50%

tw

50%

tds

50%

tch

tw

50%

tdh

50%

50%

VDD

0V

VDD

0V

VDD

0V

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