CXD2464R Просмотр технического описания (PDF) - Sony Semiconductor

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CXD2464R

Timing Generator for LCD Panels

Sony Semiconductor 

CXD2464R

Input Signal Protocol

1. Horizontal sync signal

a) A standard signal (HSYNC) should be input for the following display modes.

LCX026 : SVGA (800 × 600), VGA/NTSC (640 × 480), PC-98 (640 × 400), PAL (762 × 572)

LCX016 : Macintosh16 (832 × 624), SVGA (800 × 600), VGA/NTSC (640 × 480), PC-98 (640 × 400),

PAL (762 × 572), WIDE (832 × 480)

LCX012BL : VGA/NTSC/PAL (640 × 480), PC-98 (640 × 400)

However, since the CXD2464R requires a double speed signal as input during NTSC/PAL double-

speed display when not using the built-in double-speed controller, a simply double-speeded, 1/2 cycle,

1/2 width horizontal sync signal (HSYNC) should be input at that time.

b) The input sync signal polarity is not fixed, and is set by the serial data (HPOL).

2. Vertical sync signal

a) A sync-separated, normal-speed VSYNC should be input as the vertical sync signal.

b) The input sync signal polarity is not fixed, and is set by the serial data (VPOL).

c) The phase relationship between HSYNC and VSYNC is specified as follows for the CXD2464R.

(1) SVGA, VGA, PC-98 (LCX026)/Macintosh16, SVGA, VGA, PC-98 (LCX016)/VGA, PC-98 (LCX012BL)

HSYNC

VSYNC

Sync signal phase reference

(2) Double-speed NTSC (LCX026/LCX016/LCX012BL)

Double-speed HSYNC

VSYNC

Sync signal phase reference

(3) Double-speed PAL (LCX026/LCX016/LCX012BL)

Double-speed HSYNC

VSYNC

Sync signal phase reference

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