CXD3526GG Просмотр технического описания (PDF) - Sony Semiconductor

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CXD3526GG

Digital Signal Driver/Timing Generator

Sony Semiconductor 

CXD3526GG

(g) Host I/F serial clock input pin (HSCL)

HSCL (Pin 68) is the clock input pin used to set the I/O timing for serial data from the host. Data is taken from

the HSDA pin when the clock signal rises, and data is output to the HSDA pin when the clock signal falls.

(h) Host I/F serial I/O pin (HSDA)

This is the I/O pin for serial data from the host. It is necessary to switch the input to the HSDA (Pin 70) while

the signal level of HSCL is low.

(i) Slave address input pin (HSEL)

With this IC, it is possible to select host I/F slave address. Since a slave address is used to identify each of

these devices, this pin should be connected to VDD or Vss externally. This VDD and Vss setting drives the device

which matches the slave address input from the HSDA pin. The slave addresses of this IC used for the HSEL

(Pin 22) setting are as follows.

HSEL: 0 = 74h; 1 = 76h

(j) External ROM I/F serial clock output pin (RSCL)

RSCL (Pin 23) is the clock output pin used to set the I/O timing of serial data sent to the external EEPROM.

Data is taken from the RSDA pin when the clock signal rises, and data is output to the RSDA pin when the

clock signal falls.

(k) External ROM I/F serial I/O pin (RSDA)

This is the I/O pin for serial data sent to the external EEPROM. It is necessary to switch the input to the RSDA

(Pin 69) while the signal level of RSCL is low.

2. Pipeline Delay of the RGB and OSD Signals

The pipeline delay for the I/O of the RGB signals is 32 clock cycles of the master clock. In addition, the pipeline

delay for the OSD, YS and YM signals is 25 clock cycles of the master clock.

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