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CXD3500R

Timing Generator for LCD Panels

Sony Semiconductor 

CXD3500R

HSTP3, 2, 1, 0

These bits adjust the HST pulse start phase relative to HCK in 1-dot units.

Set these bits as follows using HSTP5 to 0: LLLLLL (LSB) as the reference.

Serial setting HCKM: L (6-dot simultaneous sampling)

HST

Reference

Reference

HCK1

HSTP5 to 0: LLLLLL (LSB)

3 clk

HSTP5 to 0: LLLLHH (LSB)

HST

Reference

Reference

HCK1

6 clk

HSTP5 to 0: LLLHHL (LSB)

11 clk

HSTP5 to 0: LLHLHH (LSB)

to LLHHHH (LSB)

HST

Reference Same hereafter using this point as the reference.

HCK1

HSTP5 to 0: LHLLLL (LSB)

Note) HCK2 is the reverse polarity of HCK1. The timings shown above are for RGT: H, HCKPOL: H and

HCKFX: L.

Serial setting HCKM: H (12-dot simultaneous sampling)

HST

Reference

Reference

HCK1

HSTP5 to 0: LLLLLL (LSB)

12 clk

6 clk

HSTP5 to 0: LLLHHL (LSB)

HST

Reference

Reference Same hereafter using this point as the reference.

HCK1

HSTP5 to 0: LLHLHH (LSB)

11 clk

to LLHHHH (LSB)

HSTP5 to 0: LHLLLL (LSB)

Note) HCK2 is the reverse polarity of HCK1. The timings shown above are for RGT: H, HCKPOL: H and

HCKFX: L.

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