CXD3500R Просмотр технического описания (PDF) - Sony Semiconductor

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CXD3500R

Timing Generator for LCD Panels

Sony Semiconductor 

CXD3500R

Horizontal direction pulses

The horizontal direction timing pulses for driving LCD panels are advanced and delayed interlinked with serial

data HP11 to 0. The reference at this time is the falling edge of the ENB1 and 2 pulses.

Except for during skip scan, the ENB1 and 2 pulse width is fixed by serial data PLSSL, and the pulse position

is determined by serial data HP11 to 0. (See the Timing Charts.) The horizontal direction pulse position for

other panels is generated by the internal counter that is reset at the ENB1 and 2 pulse fall position.

HSTW1, 0

These bits set the HST pulse width. Normally set HSTW1 and 0 to LL for 6-dot simultaneous sampling panels

(VGA, SVGA), and to HL for 12-dot simultaneous sampling panels (XGA).

HSTW1, 0

LL

LH

HL

HH

HST pulse width

12 clk

18 clk

24 clk

48 clk

HSTP5, 4

This sets the HST pulse rise position. The HST pulse rise position from the falling edge of the ENB1 and 2

pulses is as shown in the table below according to the PLSSL2, 1, 0 setting.

However, note that the HSTP5 setting is invalid when PLSSL2 to 0 (described hereafter) is set from LLL to

HLL.

Thst

ENB1, 2

HST

PLSSL2, 1, 0

LLL

LLH

LHL

LHH

HLL

HLH

HHL

HHH

Thst rise position

LL

70 clk

90 clk

116 clk

144 clk

176 clk

186 clk

202 clk

230 clk

HSTP5, 4

LH

HL

82 clk

70 clk

102 clk

90 clk

128 clk

116 clk

156 clk

144 clk

188 clk

176 clk

198 clk

210 clk

214 clk

226 clk

242 clk

254 clk

HH

82 clk

102 clk

128 clk

156 clk

188 clk

222 clk

238 clk

266 clk

Note) HST3, 2, 1, 0: LLLL

– 17 –

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