CXD3500R Просмотр технического описания (PDF) - Sony Semiconductor

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производитель

CXD3500R

Timing Generator for LCD Panels

Sony Semiconductor 

CXD3500R

2. Control data

When using the CXD3500R, set the control data corresponding to each LCD panel and video signal according

to the formats in the table below.

Address

Data

D15 D14 D13 D12 D11 D10 D9 D8 D7

D6

D5

D4

D3

D2

D1

D0

0 0 0 0 0 0 0 0 PLLP11 PLLP10 PLLP9 PLLP8 PLLP7 PLLP6 PLLP5 PLLP4

0 0 0 0 0 0 0 1 PLLP3 PLLP2 PLLP1 PLLP0 HP11 HP10 HP9 HP8

0 0 0 0 0 0 1 0 HP7 HP6 HP5 HP4 HP3 HP2 HP1 HP0

0 0 0 0 0 0 1 1 VP7 VP6 VP5 VP4 VP3 VP2 VP1 VP0

0 0 0 0 0 1 0 0 HSTW1 HSTW0 HSTP5 HSTP4 HSTP3 HSTP2 HSTP1 HSTP0

0 0 0 0 0 1 0 1 PCGU2 PCGU1 PCGU0 PCGD4 PCGD3 PCGD2 PCGD1 PCGD0

00000110 —

—

— PRGD4 PRGD3 PRGD2 PRGD1 PRGD0

0 0 0 0 0 1 1 1 set 0 PCG FRP1 FRP0 FRPP3 FRPP2 FRPP1 FRPP0

0 0 0 0 1 0 0 0 VSTFX HCKFX HCKM INV SHP3 SHP2 SHP1 SHP0

0 0 0 0 1 0 0 1 VSTPOL HCKPOL VPOL HPOL HDNPOL CLPPOL CLPW CLPP

0 0 0 0 1 0 1 0 SLCNT SLFLD SLRS CKPOL SLCK PLSSL2 PLSSL1 PLSSL0

0 0 0 0 1 0 1 1 BLKON BLKPOL FMBK MBKA4 MBKA3 MBKA2 MBKA1 MBKA0

0 0 0 0 1 1 0 0 MBKZ3 MBKZ2 MBKZ1 MBKZ0 MBKB3 MBKB2 MBKB1 MBKB0

0 0 0 0 1 1 0 1 VGAV HR DWN RGT DSP PO/MODE3 PO/MODE2 PO/MODE1

0 0 0 0 1 1 1 0 XGBK HDON HAXON VAXON set 0 set 0 set 0 SPON

00001111 —

—

—

—

—

— set 0 set 0

0 0 0 1 0 0 0 0 SLLAP LPCK SLCKL ORRS4 ORRS3 ORRS2 ORRS1 ORRS0

0 0 0 1 0 0 0 1 IRD11 IRD10 IRD9 IRD8 IRD7 IRD6 IRD5 IRD4

0 0 0 1 0 0 1 0 IRD3 IRD2 IRD1 IRD0 IRU11 IRU10 IRU9 IRU8

0 0 0 1 0 0 1 1 IRU7 IRU6 IRU5 IRU4 IRU3 IRU2 IRU1 IRU0

0 0 0 1 0 1 0 0 VRSP3 VRSP2 VRSP1 VRSP0 ORP11 ORP10 ORP9 ORP8

0 0 0 1 0 1 0 1 ORP7 ORP6 ORP5 ORP4 ORP3 ORP2 ORP1 ORP0

0 0 0 1 0 1 1 0 ORD11 ORD10 ORD9 ORD8 ORD7 ORD6 ORD5 ORD4

0 0 0 1 0 1 1 1 ORD3 ORD2 ORD1 ORD0 ORU11 ORU10 ORU9 ORU8

0 0 0 1 1 0 0 0 ORU7 ORU6 ORU5 ORU4 ORU3 ORU2 ORU1 ORU0

0 0 0 1 1 0 0 1 HAXD11 HAXD10 HAXD9 HAXD8 HAXD7 HAXD6 HAXD5 HAXD4

0 0 0 1 1 0 1 0 HAXD3 HAXD2 HAXD1 HAXD0 HAXU11 HAXU10 HAXU9 HAXU8

0 0 0 1 1 0 1 1 HAXU7 HAXU6 HAXU5 HAXU4 HAXU3 HAXU2 HAXU1 HAXU0

0 0 0 1 1 1 0 0 VAXD11 VAXD10 VAXD9 VAXD8 VAXD7 VAXD6 VAXD5 VAXD4

0 0 0 1 1 1 0 1 VAXD3 VAXD2 VAXD1 VAXD0 VAXU11 VAXU10 VAXU9 VAXU8

0 0 0 1 1 1 1 0 VAXU7 VAXU6 VAXU5 VAXU4 VAXU3 VAXU2 VAXU1 VAXU0

— or

: Setting invalid.

Note) PLLP0, HP0, VP0, HSTW0, HSTP0, PCGU0, PCGD0, PRGD0, FRPP0, SHP0, MBKA0, MBKB0,

MBKZ0, IRD0, IRU0, ORRS0, ORP0, ORD0, ORU0, HAXD0, HAXU0, VAXD0, VAXU0: LSB.

Shaded bits (PLLP0, IRU0, ORPU, ORU0 and HAXU0) are indicated for reference, and actual data

setting to these bits is invalid.

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