CS5501-BSZ Просмотр технического описания (PDF) - Cirrus Logic
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CS5501-BSZ Datasheet PDF : 54 Pages
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CS5501 CS5503
CS5501/CS5503
SWITCHING CHARACTERISTICS (continued) (TA = Tmin to Tmax; VA+, VD+ = 5V ± 10%;
VA-, VD- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF)
Parameter
Symbol Min
Typ
Max Units
SSC Mode (Mode = VD+)
Access Time
CS Low to SDATA Out
tcsd1 3/CLKIN
-
-
ns
SDATA Delay Time
SCLK Falling to New SDATA bit tdd1
-
25
100
ns
SCLK Delay Time
(at 4.096 MHz)
SDATA MSB bit to SCLK Rising tcd1
250
380
-
ns
Serial Clock
(Out)
Pulse Width High (at 4.096 MHz) tph1
-
Pulse Width Low
tpl1
-
240
300
ns
730
790
Output Float Delay
SCLK Rising to Hi-Z
tfd2
-
1/CLKIN 1/CLKIN ns
+ 100 + 200
Output Float Delay
CS High to Output Hi-Z (Note 18) tfd1
-
-
4/CLKIN ns
+200
SEC Mode (Mode = DGND)
Serial Clock (In)
fsclk
dc
-
4.2 MHz
Serial Clock (In)
Pulse Width High
Pulse Width Low
tph2
50
-
tpl2
180
-
-
ns
-
Access Time
CS Low to Data Valid (Note 19) tcsd2
-
80
160
ns
Maximum Data Delay Time
(Note 20)
SCLK Falling to New SDATA bit tdd2
-
75
150
ns
Output Float Delay
CS High to Output Hi-Z
tfd3
-
-
250
ns
Output Float Delay
SCLK Falling to Output Hi-Z
tfd4
-
100
200
ns
Notes: 18. If CS is returned high before all data bits are output, the SDATA and SCLK outputs will complete
the current data bit and then go to high impedance.
19. If CS is activated asynchronously to DRDY, CS will not be recognized if it occurs when DRDY is high
for 4 clock cycles. The propagation delay time may be as great as 4 CLKIN cycles plus 160 ns.
To guarantee proper clocking of SDATA when using asychronous CS, SCLK(i) should not be taken
high sooner than 4 CLKIN cycles plus 160ns after CS goes low.
20. SDATA transitions on the falling edge of SCLK(i).
CAL
SC1, SC2
tscs tsch
VALID
Calibration Control Timing
CLKIN
tsls
SLEEP
Sleep Mode Timing for
Synchronization
CS
tfd1
SDATA
Output Float Delay
SSC Mode (Note 19)
88
DS31F54
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