CS5501 Просмотр технического описания (PDF) - Cirrus Logic

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CS5501

Non-aliasing, 16- & 20-bit A/D Converters

Cirrus Logic 

CS5501 CS5503

CS5501/CS5503

represents the gain slope for the input to output

transfer function of the converter. In unipolar

mode the calibration microcontroller determines

the slope factor by dividing the span between the

zero point and the full scale point by the total

resolution of the converter (216 for the CS5501,

resulting in 65,536 segments or 220 for the

CS5503, resulting in 1,048,578 segments). In bi-

polar mode the calibration microcontroller divides

the span between the zero point and the full scale

point into 524,288 segments for the CS5503 and

32,768 segments for the CS5501. It then extends

the measurement range 524,288 segments for the

CS5503, 32,768 segments for the CS5501, below

the zero scale point to achieve bipolar measure-

ment capability. In either unipolar or bipolar

modes the calculated slope factor is saved and

later used to calculate the binary output code

when an analog signal is present at the AIN pin

during measurement conversions.

Figure 9). System calibration performs the same

slope factor calculations as self cal but uses volt-

age values presented by the system to the AIN pin

for the zero scale point and for the full scale

point. Table 2 depicts the calibration modes

available. Two system calibration modes are

listed. The first mode offers system level calibra-

tion for system offset and for system gain. This is

a two step calibration. The zero scale point (sys-

tem offset) must be presented to the converter

first. The voltage that represents zero scale point

must be input to the converter before the calibra-

tion step is initiated and must remain stable until

the step is complete. The DRDY output from the

converter will signal when the step is complete by

going low. After the zero scale point is calibrated,

the voltage representing the full scale point is in-

put to the converter and the second calibration

step is initiated. Again the voltage must remain

stable throughout the calibration step.

System calibration allows the A/D converter to This two step calibration mode offers another cali-

compensate for system gain and offset errors (see bration feature. After a two step calibration

VREF sys

Transducer

Analog

MUX

A0 A1

Signal

Conditioning

Circuitry

CS5501

SCLK

CS5503 SDATA

CAL SC1 SC2

Figure 9. System Calibration

CLK

DATA

µC

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

CAL SC1 SC2 Cal Type

ZS Cal FS Cal Sequence Calibration Time

0

0

Self-Cal

AGND VREF One Step

3,145,655/fclk

1

1 System Offset AIN

0

1 & System Gain

-

-

1st Step

1,052,599/fclk

AIN

2nd Step

1,068,813/fclk

1

0 System Offset AIN VREF One Step

2,117,389/fclk

* DRDY remains high throughout the calibration sequence. In Self-Cal mode (SC1 and SC2 low) DRDY

falls once the CS5501 or CS5503 has settled to the analog input. In all other modes DRDY falls

immediately after the calibration term has been determined.

Table 2. Calibration Control

1188

DS31F54

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