CDB5501 Просмотр технического описания (PDF) - Cirrus Logic
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CDB5501 Datasheet PDF : 54 Pages
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CS5501 CS5503
CS5501/CS5503
0
0
-20
-20
-40
-40
CLKIN = 4 MHz
-60
-60
CLKIN = 2 MHz
-80
-80
-100
0
-100
20
40
60
80
100
0
CLKIN=1 MHz
20
40
60
80
100
Frequency (Hz)
Frequency (Hz)
a. Averaging (Integrating) Filter Response (tavg = 100 ms)
b. 6-Pole Gaussian Filter Response
Figure 2. Filter Responses
A/D Conversion Technique Overview" in the ap-
plication note section of the data book. The
application note discusses the delta-sigma modu-
lator and some aspects of digital filtering.
OVERVIEW
As shown in the block diagram on the front page
of the data sheet, the CS5501/CS5503 can be seg-
mented into five circuit functions. The heart of the
chip is the charge balance A/D converter (16-bit
for the CS5501, 20-bit for the CS5503). The con-
verter and all of the other circuit functions on the
chip must be driven by a clock signal from the
clock generator. The serial interface logic outputs
the converted data. The calibration microcontrol-
ler along with the calibration SRAM (static
RAM), supervises the device calibration. Each
segment of the chip has control lines associated
with it. The function of each of the pins is de-
scribed in the pin description section of the data
sheet.
Clock Generator
The CS5501/CS5503 both include gates which
can be connected as a crystal oscillator to provide
the master clock signal for the chip. Alternatively,
an external (CMOS compatible) clock can be in-
put to the CLKIN pin as the master clock for the
device. Figure 3 illustrates a simple model of the
on-chip gate oscillator. The gate has a typical
transconductance of 1500 µmho. The gate model
includes 10 pf capacitors at the input and output
pins. These capacitances include the typical stray
capacitance of the pins of the device. The on-chip
CLKIN
3
10pF
R1 500 k Ω
CLKOUT
2
10pF
g 1500 umho
m
C1 *
Y1
C2 *
* See Table 1
Figure 3. On-chip Gate Oscillator Model
1122
DS31F54
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