CS5501 Просмотр технического описания (PDF) - Cirrus Logic

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CS5501

Non-aliasing, 16- & 20-bit A/D Converters

Cirrus Logic 

CS5501 CS5503

CS5501/CS5503

SWITCHING CHARACTERISTICS (continued) (TA = Tmin to Tmax;

VA+, VD+ = 5V ± 10%; VA-, VD- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF)

Parameter

Symbol Min

Typ

Max Units

AC Mode (Mode = VD-) CS5501 only

Serial Clock (In)

fsclk

dc

-

4.2 MHz

Serial Clock (In)

Pulse Width High

Pulse Width Low

tph3

50

-

tpl3

180

-

-

ns

-

ns

Set-up Time

CS Low to SCLK Falling

tcss

-

20

40

ns

Maximum Data Delay Time SCLK Fall to New SDATA bit

tdd3

-

90

180

ns

Output Float Delay

CS High to Output Hi-Z (Note 21) tfd5

-

100

200

ns

Notes: 21. If CS is returned high after an 11-bit data packet is started, the SDATA output will continue to output

data until the end of the second stop bit. At that time the SDATA output will go to high impedance.

DRDY

CS

SCLK(i)

SDATA

t css

t ph3

t dd3

Hi-Z

START BIT8 BIT9

t pl3

t fd5

BIT6 BIT7 STOP1 STOP2 Hi-Z

High Byte

Low Byte

AC MODE Timing Relationships (CS5501 only)

1100

DS31F54

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