RF2915 Просмотр технического описания (PDF) - RF Micro Devices
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RF2915 Datasheet PDF : 18 Pages
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RF2915
RF2915 Theory of Operation and Application Information
11
The RF2915 is part of a family of low-power RF trans-
ceiver IC’s that was developed for wireless data com-
munication devices operating in the European 433MHz
to 868MHz ISM band, and 915MHz U.S. ISM band.
This IC has been implemented in a 15GHz silicon
bipolar process technology that allows low-power
transceiver operation in a variety of commercial wire-
less products.
In its basic form, the RF2915 can be implemented as a
two-way half-duplex FSK transceiver with the addition
of some crystals, filters, and passive components. The
RF2915 is designed to interface with common PLL IC’s
to form a multi-channel radio. The receiver IF section is
optimized to interface with low-cost 10.7MHz ceramic
filters and has a 3dB bandwidth of 25MHz and can still
be used (with lower gain) at higher frequencies with
other types of filters. The PA output and LNA input are
available on separate pins and are designed to be con-
nected together through a DC blocking capacitor. In the
transmit mode, the PA will have a 50Ω impedance and
the LNA will have a high impedance. In the receive
mode, the LNA will have a 50Ω impedance and the PA
will have a high impedance. This eliminates the need
for a TX/RX switch, and allows for a single RF filter to
be used in transmit and receive modes. Separate
access to the PA and LNA allows the RF2915 to inter-
face with external components such as a high power
PA, lower NF LNA, upconverters, and downconverters,
for a variety of implementations.
FM/FSK SYSTEMS
The MOD IN pin drives an internal varactor for modu-
lating the VCO. This pin can be driven with a voltage
level needed to generate the desired deviation. This
voltage can be carried on a DC bias to select desired
slope (deviation/volt) for FM systems. Or, a resistor
divider network referenced to VCC or ground can
divide down logic level signals to the appropriate level
for a desired deviation in FSK systems.
On the receiver demodulator, the DATA OUT pin is
generally used as a data slicer providing logic level out-
puts. However, by lightly loading the output with a
resistive load, the bandwidth of the data slicer can be
limited, and an analog signal recovered. A resistance
value of around 10kΩ to 15kΩ is sufficient. The digital
output is generated by a data slicer that is DC-coupled
differentially to the demodulator. An on-chip 1.6MHz
RC filter is provided at the demodulator output to filter
the undesirable 2xIF product. This balanced data slicer
has a speed advantage over a conventional adapter
11-118
data slicer where a large capacitor is used to provide
DC reference for the bit decision. Since a balanced
data slicer does not have to charge a large capacitor,
the RF2915 exhibits a very fast response time. For
best operation of the on-chip data slicer, FM deviation
needs to exceed the carrier frequency error anticipated
between the receiver and transmitter with margin.
The data slicer itself is a transconductance amplifier,
and the DATA OUT pin is capable of driving rail-to-rail
output only into a very high impedance and a small
capacitance. The amount of capacitance will determine
the bandwidth of DATA OUT. In a 3pF load, the band-
width is in excess of 500kHz. The rail-to-rail output of
the data slicer is also limited by the frequency deviation
and bandwidth of IF filters. With the 180kHz bandwidth
filters on the evaluation boards, the rail-to-rail output is
limited to less than 140kHz. Choosing the right IF
bandwidth and deviation versus data rate (mod index)
is important in evaluating the applicability of the
RF2915 for a given data rate.
The primary consideration when directly modulating
the VCO is the data rate versus PLL bandwidth. The
PLL will track out the modulation to the extent of its
bandwidth, which distorts the modulating data. There-
fore, the lower frequency components of the modulat-
ing data should be five to 10 times the loop bandwidth
to minimize the distortion. The lower frequency compo-
nents are generated by long strings of 1’s and 0’s in
data stream. By limiting the number of consecutive,
same bits, lower frequency components can be set. In
addition, the data stream should be balanced to mini-
mize distortion. Using a coding pattern such as
Manchester is highly recommended to optimize system
performance.
The PLL loop bandwidth is important in several system
parameters. For example, switching from transmit to
receive requires the VCO to retune to another fre-
quency. The switching speed is proportional to the loop
bandwidth: the higher the loop bandwidth, the faster
the switching times. Phase noise of the VCO is another
factor. Phase noise outside the bandwidth is because
of the VCO itself, rather than a crystal reference. The
design trade-offs must be made here in selecting a
PLL loop bandwidth with acceptable phase noise and
switching characteristics, as well as minimal distortion
of the modulation data.
Rev A7 001011
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