ACS401 Просмотр технического описания (PDF) - Semtech Corporation
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ACS401 Datasheet PDF : 8 Pages
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Bandwidth
per channel
32 kHz
64 kHz
128 kHz
16 kHz
32 kHz
64 kHz
32 kHz
16 kHz
No of
Channels
4
2
1
4
2
1
1
1
BCP
128 kHz
128 kHz
128 kHz
64 kHz
64 kHz
64 kHz
32 kHz
16 kHz
‘Double’ mode - XTAL= 9.216 MHz
Bandwidth
per channel
16 kHz
32 kHz
64 kHz
16 kHz
32 kHz
16 kHz
No of
Channels
4
2
1
2
1
1
BCP
64 kHz
64 kHz
64 kHz
32 kHz
32 kHz
16 kHz
Power consumption will be minimised by choosing the lowest
BCP.
Control Signals
The control signal set XI(1:2) are oversampled at a rate of:
XTAL / 18,432 (Hz) in ‘standard’ mode
XTAL / 36,864 (Hz) in ‘double’ mode
The signals are filtered by a 4-bit filter ensuring that the data
applied to these inputs is not easily corrupted. These signals may
be used for control data regarded as critical. The sampling
frequency and filtering dictates a minimum Low or High time for
data applied to inputs XI(1:2) of:
> (18,432 * 4) / XTAL(s) in ‘standard’ mode
> (36,864 * 4) / XTAL (s) in ‘double’mode
Therefore, with the recommended XTAL frequency of 9.216 MHz
and ‘standard’ mode operation, the minimum High or Low time for
data applied to XI(1:2) for successful propagation is 8 ms.
The logic status of XI(1:2) is propagated over the link and appears
at the far-end at XO(1:2). When the devices are out of lock
(DCDB = High), then XO1 = XO2 = High.
Transmission Clock TxCL
The ACS401 gives a choice between internally and externally
generated transmission clocks. When the CKC pin is held Low,
TxCL is configured as an output producing a clock at the
frequency defined by DR(1:4). When the CKC pin is held High,
TxCL is configured as an input, and will accept an externally
produced transmission clock with a tolerance of up to 500 ppm
with respect to the transmission rate determined by DR(1:4). Data
is latched into the device on the rising edge of the TxCL clock
independent of internal or external TxCL generation.
It is possible to propagate asynchronous data through the link.
The TxCL clock will over-sample the data at the rate defined by
DR(1-4). The choice of TxCLclock frequency dictates the sample
rate of the asynchronous data appearing at the input TxD, and
consequently the jitter on the output RxD at the far-end.
Example:
DR4/3/2/1
CKC
Transmission data rate
TxD data rate
= 1000
=0
= 128 kbps
= 19.2 kbps
With this set-up the over-sample factor is 128 / 19.2 = 6.67, giving
an effective jitter of ~15 %.
Receive Clock RxCL
In synchronous mode, data is valid on the rising edge of RxCL
clock (see Figure 2. Timing diagrams). To ensure that the
average receive frequency is the same as the transmitted
frequency, RxCL is generated from a Digital Phase-Lock Loop
(DPLL) system (except where master mode has been selected).
The DPLLmakes periodic corrections to the output RxCL clock to
compensate for differences in the XTAL frequencies. In the case
of an externally supplied transmission clock TxCL, compensation
is also made for differences in frequency between the supplied
data clock and the selected clock rate defined by DR(1:4). The
DPLL is adaptive and will minimise the frequency of correction
and jitter, where the XTALfrequency and transmission clocks are
tightly toleranced.
Diagnostic Modes
The ACS401 has eight diagnostic modes controlled by DM(1:3).
These are shown in the following table.
Diagnostic Mode
Full-duplex
Full-duplex
Remote loopback
Full-duplex
Local loopback
Full-duplex slave
Full-duplex master
Full-duplex
Lock
Drift
Memory
Active
Random
Drift
Active
Drift
Active
DM3
0
0
0
0
1
1
1
1
DM2
0
0
1
1
0
0
1
1
DM1
0
1
0
1
0
1
0
1
Full-duplex
In the full-duplex configuration, the RxCL clock of both devices
tracks the average frequency of the TxCL clock of the opposite
end of the link. The receiving Digital Phase-Lock Loop (DPLL)
system makes periodic adjustments to the RxCL clock to ensure
that the average frequency is exactly the same as the far-end
TxCL clock. In summary, each TxCL is an independent master
clock and each RxCL a slave of the far-end TxCL clock.
Full-duplex slave
In slave mode the TxCL and the RxCL clock is derived from the
TxCL clock of the far-end of the link, such that the average
frequency is exactly the same. Clearly, it is essential that only one
modem is configured in slave mode at a time. The CKC pin is
overridden such that TxCL is always configured as an output.
Since only one device in the modem pair may be configured in
slave mode, the mode also selects active lock.
Full-duplex master
In master mode the RxCL clock is internally generated from the
local TxCL clock. The local TxCLclock producing the RxCLclock
may be internally or externally generated. Master mode is only
valid if the far-end device is configured in slave mode or if the far-
end TxCLclock is derived from the far-end RxCLclock. Only one
modem in the communicating pair may be configured as a master.
Local Loopback
In local loopback mode, TxD data is looped back inside the near-
end modem and is output at its own RxD output. The data is also
sent to the far-end modem and synchronisation between the
modems is maintained.
In local loopback mode data received from the far-end device is
ignored, except to maintain lock. If concurrent requests occur for
local and remote loopback, local loopback is selected.
The local loop diagnostic mode is used to test data flow up to, and
back from, the local ACS401 and does not test the integrity of the
link itself. Therefore, local loopback operates independently of
synchronisation with a second modem (DCDB may be High or
Low).
Remote Loopback
In remote loopback mode, the near-end modem sends a request
to the far-end modem to loopback its received data, thus returning
the data. The far-end modem also outputs the received data at its
RxD. Both modems are exercised completely, as well as the
LASERs/LEDs and the fiber optic link. The remote loopback test
is normally used to check the integrity of the entire link from the
near-end (initiating modem).
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