CDB53L32A Просмотр технического описания (PDF) - Cirrus Logic
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CDB53L32A Datasheet PDF : 40 Pages
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CS53L32A
4.7 MASTER MODE
Interface Control Register (address 02h)
7
RESERVED
6
MCLKDIV
5
RATIO1
4
RATIO0
3
MASTER
2
DIF2
1
DIF1
0
DIF0
Access:
R/W in Two Wire Mode and write only in SPI.
Default:
0 - Slave Mode
Function:
Configures the device for master or slave operation when in Control Port mode.
MASTER
0
1
MODE
Slave Mode
Master Mode
Table 6. Master/Slave Mode Selection
4.8 DIGITAL INTERFACE FORMAT
Interface Control Register (address 02h)
7
RESERVED
6
MCLKDIV
5
RATIO1
4
RATIO0
3
MASTER
2
DIF2
Access:
R/W in Two Wire Mode and write only in SPI.
1
DIF1
0
DIF0
Default:
0 - Format 0 (I2S, up to 24-bit data, Data valid on positive edge of SCLK)
Function:
The required relationship between the Left/Right clock, serial clock and serial data is defined by the
Digital Interface Format and the options are detailed in Figures 18 through 21.
DIF2
0
0
0
0
1
1
1
1
DIF1
0
0
1
1
0
0
1
1
DIF0
DESCRIPTION
0 I2S, up to 24-bit Data, Data valid on positive edge of SCLK
1 Left Justified, up to 24-bit Data, Data valid on positive edge of SCLK
0 Reserved
1 Right Justified, 16-bit Data, Data valid on positive edge of SCLK
0 Right Justified, 24-bit Data, Data valid on positive edge of SCLK
1 Right Justified, 18-bit Data, Data valid on positive edge of SCLK
0 Right Justified, 20-bit Data, Data valid on positive edge of SCLK
1 Reserved
Table 7. Digital Interface Format
Format
0
1
2
3
4
5
6
7
FIGURE
18
19
-
18
19
20
21
-
DS513F1
21
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