6277 Просмотр технического описания (PDF) - Allegro MicroSystems
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6277 Datasheet PDF : 12 Pages
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6277
8-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIVER
TIMING REQUIREMENTS and SPECIFICATIONS
(Logic Levels are VDD and Ground)
C
CLOCK
50%
SERIAL
DATA IN
SERIAL
DATA OUT1.
A
B
DATA
50%
tp
50%
SERIAL
DATA OUT.2
D
LATCH
ENABLE
DATA
tp
50%
DATA
E
50%
OUTPUT
ENABLE
LOW = ALL OUTPUTS ENABLED
OUT N
OUTPUT
ENABLE
OUT N
tp
HIGH = OUTPUT OFF
50%
DATA
LOW = OUTPUT ON
Dwg. WP-029-3
HIGH = ALL OUTPUTS DISABLED (BLANKED)
50%
F
t en(BQ)
t dis(BQ)
tf
tr
90%
DATA
10%
Dwg. WP-030-1
A. Data Active Time Before Clock Pulse
(Data Set-Up Time), tsu(D) .......................................... 60 ns
B. Data Active Time After Clock Pulse
(Data Hold Time), th(D) .............................................. 20 ns
C. Clock Pulse Width, tw(CK) ............................................... 50 ns
D. Time Between Clock Activation
and Latch Enable, tsu(L) ............................................ 100 ns
E. Latch Enable Pulse Width, tw(L) ................................... 100 ns
F. Output Enable Pulse Width, tw(OE) ................................ 4.5 µs
NOTE – Timing is representative of a 10 MHz clock.
Significantly higher speeds are attainable.
— Max. Clock Transition Time, tr or tf .............................. 10 µs
Information present at any register is transferred to the
respective latch when the LATCH ENABLE is high (serial-to-
parallel conversion). The latches will continue to accept new
data as long as the LATCH ENABLE is held high. Applica-
tions where the latches are bypassed (LATCH ENABLE tied
high) will require that the OUTPUT ENABLE input be high
during serial data entry.
When the OUTPUT ENABLE input is high, the output
source drivers are disabled (OFF). The information stored in the
latches is not affected by the OUTPUT ENABLE input. With
the OUTPUT ENABLE input low, the outputs are controlled by
the state of their respective latches.
115 Northeast Cutoff, Box 15036
6
Worcester, Massachusetts 01615-0036 (508) 853-5000
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