AK4523VF Просмотр технического описания (PDF) - Asahi Kasei Microdevices
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AK4523VF Datasheet PDF : 20 Pages
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ASAHI KASEI
[AK4523]
n Audio Serial Interface Format
Data is shifted in/out the SDTI/SDTO pins using SCLK and LRCK inputs. Four serial data modes selected by the DIF0 and
DIF1 pins are supported as shown in Table 2. In all modes the serial data has MSB first, 2’s compliment format. The data
is clocked out on the falling edge of SCLK and latched on the rising edge. For mode 3, if SCLK is 32fs, then the least
significant bits will be truncated.
Mode
0
1
2
3
DIF1
0
0
1
1
DIF0
0
1
0
1
SDTO (ADC)
20bit, MSB justified
20bit, MSB justified
20bit, MSB justified
IIS (I2S)
SDTI (DAC)
16bit, LSB justified
20bit, LSB justified
20bit, MSB justified
IIS (I2S)
L/R
SCLK (Slave)
H/L
³ 32fs
H/L
³ 40fs
H/L
³ 40fs
L/H
32fs or ³ 40fs
Table 2. Serial Data Modes
LRCK(i)
0 1 23
SCLK(i:32fs)
9 10 11 12 13 14 15 0 1 2
SDTO(o)
19 18 17
11 10 9 8 7 6 5 4 19 18 17
9 10 11 12 13 14 15 0 1
11 10 9 8 7 6 5 4 19
SDTI(i)
15 14 13
7 6 5 4 3 2 1 0 15 14 13
7 6 5 4 3 2 1 0 15
0 1 23
SCLK(i:64fs)
SDTO(o)
19 18 17
17 18 19 20
3 21 0
30 31 0 1 2 3
17 18 19 20
19 18 17
3210
31 0 1
19
SDTI(i)
Don’t Care 15 14 13 12 11 2 1 0 Don’t Care
SDTO-19:MSB, 0:LSB; SDTI-15:MSB, 0:LSB
Lch Data
Figure 1. Mode 0 Timing
15 14 13 12 11 2 1 0
Rch Data
LRCK(i)
012
SCLK(i:64fs)
12 13 14
20 21
31 0 1 2
12 13 14
20 21
31 0 1
SDTO(o)
19 18
876
0
19 18
876
0
19
SDTI(i)
Don’t Care 19 18
12 11
19:MSB, 0:LSB
Lch Data
1 0 Don’t Care
Figure 2. Mode 1 Timing
19 18
12 11
Rch Data
10
M0021-E-03
- 11 -
1999/12
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