XRD8794AB Просмотр технического описания (PDF) - Exar Corporation

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XRD8794AB

XRD8794AB Application Board

Exar Corporation 

XRD8794AB

JP7. Using JP8 the positive reference can be

shorted to AVDD and using JP6 the negative refer-

ence can be shorted to AGND. If JP6 and JP8 are in,

remove JP5, JP7 and the dual op-amp. This avoids

potentially loading the power supplies with 50Ω,

shorting the op-amp output or shorting the external

reference. Note that VRT must be more positive than

VRB, since the positive reference voltage must be

greater than the negative reference voltage on chip.

4. INPUT SIGNAL GENERATOR - A clean, low distor-

tion sine wave generator is used as a signal source.

A band pass filter is sometimes required to further re-

duce harmonics and band limit noise as shown. The

BNC coax connector labeled AIN accepts the analog

input. An op amp (AD843) is used to amplify this in-

put and provide low source impedance to drive the

A/D under test. This input can be used for single en-

ded inputs or applying a DC offset for level shifting

the Dither input. JP2 50Ω terminates this input. The

socket has a standard 741 type pin out which allows

experimentation with alternative amplifiers.

5. DITHER INPUT SIGNAL GENERATOR - The cross

plot test configuration (described later) requires a

triangle wave signal source. This signal is added

through the BNC connector labeled DITHER (an in-

verting input with gain of 1/20). JP1 connects this in-

put to ground via a 50Ω resistor.

6. OSCILLOSCOPE - The output of a reconstruction

DAC, TP4, is used to drive the vertical input of the os-

cilloscope for manual linearity testing using the

“cross plot” method. The reconstruction DAC is sim-

ply a resistor implementation using R15 through

R19.

7. DSP - Evaluation of dynamic and static performance

is done by external processing devices that perform

histogram and harmonic analysis to determine char-

acteristics like linearity, noise, distortion, intermo-

dulation effects, etc. The data is available at the 28

pin connector labelled D0 through D11. Each output

pin is complemented by a ground pin. The external

clock output is available on two pins labelled PTS.

The output data on the 28 pin connector is valid when

the PTS clock is high.

Rev. 1.00

5

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