STK15C68 Просмотр технического описания (PDF) - Cypress Semiconductor
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STK15C68 Datasheet PDF : 15 Pages
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STK15C88
Software Controlled STORE/RECALL Cycle
The software controlled STORE/RECALL cycle follows. [11, 12]
Parameter
Alt
tRC
tSA[11]
tCW[11]
tHACE[7, 11]
tRECALL
tAVAV
tAVEL
tELEH
tELAX
Description
STORE/RECALL Initiation Cycle Time
Address Setup Time
Clock Pulse Width
Address Hold Time
RECALL Duration
25 ns
Min
Max
25
0
20
20
20
Switching Waveforms
Figure 10. CE Controlled Software STORE/RECALL Cycle [12]
45 ns
Unit
Min Max
45
ns
0
ns
30
ns
20
ns
20
μs
ADDRESS
CE
OE
tRC
ADDRESS # 1
tSA
tSCE
tHACE
tRC
ADDRESS # 6
DQ (DATA)
DATA VALID
t / t STORE RECALL
HIGH IMPEDANCE
DATA VALID
Notes
11. The software sequence is clocked on the falling edge of CE without involving OE (double clocking will abort the sequence).
12. The six consecutive addresses must be read in the order listed in the Mode Selection table. WE must be HIGH during all six consecutive cycles.
Document Number: 001-50593 Rev. **
Page 11 of 15
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