CYM1861 Просмотр технического описания (PDF) - Cypress Semiconductor
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CYM1861 Datasheet PDF : 7 Pages
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PRELIMINARY
CYM1861
Switching Characteristics Over the Operating Range[3]
Parameter
Description
READ CYCLE
tRC
tAA
tOHA
tACS
tDOE
tLZOE
tHZOE
tLZCS
tHZCS
tPD
WRITE CYCLE[6]
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CS LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CS LOW to Low Z[4]
CS HIGH to High Z[4, 5]
CS HIGH to Power-Down
tWC
tSCS
tAW
tHA
tSA
tPWE
tSD
tHD
tLZWE
tHZWE
Write Cycle Time
CS LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
WE LOW to High Z[5]
Shaded area contains advance information.
1861-25
Min.
Max.
1861-35
Min.
Max.
Unit
25
35
ns
25
35
ns
3
3
ns
25
35
ns
15
18
ns
0
0
ns
12
15
ns
3
3
ns
12
15
ns
25
35
ns
25
35
ns
20
30
ns
20
30
ns
3
3
ns
2
2
ns
20
30
ns
15
20
ns
2
2
ns
3
3
ns
0
12
0
15
ns
Switching Waveforms
Read Cycle No. 1 [7,8]
t RC
ADDRESS
DATA OUT
tAA
tOHA
PREVIOUS DATA VALID
DATA VALID
1861–5
Notes:
3. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
4. At any given temperature and voltage condition, tHZCS is less than tLZCS for any given device. These parameters are guaranteed and not 100% tested.
5. tHZCS and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured ±500 mV from steady-state voltage.
6. The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
7. WE is HIGH for read cycle.
8. Device is continuously selected, CS = VIL, and OE= VIL.
4
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