ADP3510ARU Просмотр технического описания (PDF) - Analog Devices
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ADP3510ARU Datasheet PDF : 16 Pages
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ADP3510
Battery Voltage Monitoring
The battery voltage can be monitored at MVBAT during charging
and discharging to determine the condition of the battery. An inter-
nal resistor divider is connected to BATSNS when both the
baseband processor and the crystal oscillator are powered up. To
enable MVBAT, both PWRONIN and TCXOEN must be high.
The ratio BATSNS/MVBAT of the voltage divider is set to 3.0.
The divider will be disconnected from the battery when the
baseband processor is powered down.
Charge Detection
The ADP3510 charger block has a detection circuit that determines
if an adapter has been applied to the CHRIN pin. If the adapter
voltage exceeds the battery voltage by 260 mV, the CHRDET
output will go high. If the adapter is then removed or the voltage
at the CHRIN pin drops to around 190 mV above the BATSNS
pin, then CHRDET goes low.
APPLICATION INFORMATION
Input Capacitor Selection
For the input (VBAT and VBAT2) of the ADP3510, a local
bypass capacitor is recommended. Use a 10 mF, low ESR capacitor.
Multilayer ceramic chip (MLCC) capacitors provide the best
combination of low ESR and small size but may not be cost
effective. A lower cost alternative may be to use a 10 mF tantalum
capacitor with a small (1 mF to 2 mF) ceramic in parallel.
A separate input for the IO LDO is supplied for additional
bypassing or filtering. The IO LDO has VBAT2 as its input.
LDO Capacitor Selection
The performance of any LDO is a function of the output capacitor.
The core, memory, IO, and analog LDOs require a 2.2 mF capaci-
tor, and the TCXO LDO requires a 0.22 mF capacitor. Larger
values may be used, but the overshoot at startup will increase
slightly. If a larger output capacitor is desired, be sure to check that
the overshoot and settling time are acceptable for the application.
All the LDOs are stable with a wide range of capacitor types and
ESR (any CAP technology). The ADP3510 is stable with extremely
low ESR capacitors (ESR ~ 0), such as multilayer ceramic
capacitors, but care should be taken in their selection. Note that
the capacitance of some capacitor types show wide variations
over temperature or with dc voltage. A good quality dielectric
capacitor, X7R or better, is recommended.
The RTC LDO can have a rechargeable coin cell or an electric
double-layer capacitor as a load, but an additional 0.1 mF ceramic
capacitor is recommended for stability and best performance.
RESET Capacitor Selection
RESET is held low at power-up. An internal power-good signal
starts the reset delay when the IO LDO is up. The delay is set
by an external capacitor on RESCAP:
tRESET = 1.5 ms / nF ¥ CRESCAP
(5)
A 100 nF capacitor will produce a 150 ms reset delay. The
current capability of RESET is minimal (a few hundred nA)
when VIO is off to minimize power consumption. When VIO is
on, RESET is capable of driving 500 mA.
Power-On Delay Capacitor Selection
The PDCAP sets the interval that the VAN and VIO LDOs are
discharged. To ensure that the baseband processor is properly
reset, the VIO and VAN LDOs should be fully discharged before
power is reapplied. The discharge time can be estimated using:
tPD = 900 ¥ COUT SEC
(6)
where tPD is the discharge time, and COUT is the VIO or
VAN LDO output capacitor value.
The power-on delay is set by an external capacitor on PDCAP.
For worst-case delay:
ms
tPD = 0.3 nF ¥ CPDCAP or
nF
CPDCAP = tPD ¥ 3.33 ms
(7)
So, for a 2.2 mF output capacitor, the required delay is about 2 ms.
This results in a 6.8 nF PDCAP value.
Setting the Charge Current
The ADP3510 is capable of charging both lithium ion and
NiMH batteries. For NiMH batteries, the charge current is
limited by the adapter. For lithium ion batteries, the charge
current is programmed by selecting the sense resistor, R1.
The lithium ion charge current is calculated using:
ICHR
=
VSENSE
R1
172 mV
= R1
(8)
Where VSENSE is the high current limit threshold voltage.
Or, if the charge current is known, R1 can be found:
R1
=
VSENSE
ICHR
172 mV
= ICHR
(9)
Similarly the trickle charge current and the end of charge current
can be calculated:
ITRICKLE
=
VSENSE
R1
15 mV
= R1
IEOC
=
VSENSE
R1
=
12 mV
R1
(10)
Example: Assume a 850 mA-H capacity lithium ion battery and
a 1 C charge rate. R1 = 200 m⍀. Then ITRICKLE = 75 mA and
IEOC = 60 mA.
Appropriate sense resistors are available from the following
vendors:
Vishay Dale
IRC
Panasonic
Charger FET Selection
The type and size of the pass transistor is determined by the
threshold voltage, input-output voltage differential, and the
charge current. The selected PMOS must satisfy the physical,
electrical, and thermal design requirements.
–14–
REV. 0
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