74ABT821 Просмотр технического описания (PDF) - NXP Semiconductors.
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74ABT821 Datasheet PDF : 16 Pages
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NXP Semiconductors
74ABT821
10-bit D-type flip-flop; positive-edge trigger; 3-state
VI
OE input
GND
3.5 V
output
LOW-to-OFF
OFF-to-LOW
VOL
output
VOH
HIGH-to-OFF
OFF-to-HIGH
GND
VM
tPLZ
tPZL
tPHZ
VOL + 0.3 V
VOH − 0.3 V
VM
tPZH
VM
outputs
enabled
outputs
disabled
outputs
enabled
001aal299
Fig 6.
VM = 1.5 V.
VOL and VOH are typical voltage output levels that occur with the output load.
3-state output (Qn) enable and disable times
Vl
Dn input
GND
Vl
CP input
GND
VM
VM
tsu(H) th(H)
VM
VM
VM
tsu(L) th(L)
VM
001aac738
Fig 7.
VM = 1.5 V
The shaded areas indicate when the input is permitted to change for predictable output
performance.
Set-up and hold times data input (Dn) to clock (CP)
74ABT821_3
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 03 — 25 February 2010
© NXP B.V. 2010. All rights reserved.
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