CXD2073S Просмотр технического описания (PDF) - Sony Semiconductor
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CXD2073S Datasheet PDF : 11 Pages
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CXD2073S
Pin Description
Pin No.
1
2
Symbol
PLVD
PLVS
3 CLPEN
4 CLPO
5 ADIN
6 ADVS
7 ADVD
8 ACO
9 DAVD
10 AYO
11 DAVS
12 VRF
13 VG
14 VB
15 IRF
16 INIT
17 MOD2
18 MOD1
19 APCN
20 TST3
21 DVSS
22 DVDD
23 DVDD
24 DVSS
25 TST2
26 TST1
27 FIN
28 CKSL
29 CPO
30 VCV
I/O
Description
— Analog power supply for PLL (+5V)
— Analog ground for PLL
Clamp enable
I
L: Clamp function is enabled. Set to L when the internal clamp is used.
H: Clamp function is disabled. Set to H when the internal clamp is not used.
O
Connect to ADIN when clamp circuit is used.
Leave this pin open when clamp circuit is not used.
I Comb filter analog input (A/D converter input)
— Analog ground for A/D converter
— Analog power supply for A/D converter (+5V)
O Analog chroma signal output
— Analog power supply for D/A converter (+5V)
O Analog luminance signal output
— Analog ground for D/A converter
I D/A converter reference voltage setting. Sets the full-scale value for D/A converter.
O Connect to DAVD via a capacitor of approximately 0.1µF.
O Connect to DAVS via a capacitor of approximately 0.1µF.
O Connect a resistor of 16 times (16R) that of the output resistor "R" of AYO pin.
I Test. Normally, fix to Low.
Y/C separation status setting pins
I
MOD2 MOD1
L
L Adaptive processing mode
L
H BPF separation fixed mode
I
H
L Y through mode
H
H Simple comb mode
Aperture compensation switching
I
L: Aperture compensation OFF
H: Aperture compensation ON
O Test. Normally, leave this pin open.
— Digital ground
— Digital power supply (+5V)
— Digital power supply (+5V)
— Digital ground
O Test. Normally, leave this pin open.
I Test. Normally, fix to Low.
I
Clock input. Input burst-locked clock. Input fsc when the PLL is used. Input 4fsc
when the PLL is not used.
PLL control.
I
L: When the PLL is not used. The 4fsc clock input to FIN is supplied internally.
H: When the PLL is used. The 4fsc clock from VCO oscillation output is
supplied internally.
O
Phase comparison output for the internal PLL. Leave open when the PLL is not
used.
I
VCO oscillation control voltage input for the internal PLL. Connect to PLVS when
the PLL is not used.
–3–
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