CY7C1041CV33-10ZI Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C1041CV33-10ZI Datasheet PDF : 12 Pages
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CY7C1041CV33
Thermal Resistance[3]
Parameter
Description
Test Conditions
ΘJA Thermal Resistance (Junction to Ambient) Test conditions follow standard
ΘJC
Thermal Resistance (Junction to Case)
test methods and procedures for
measuring thermal impedance,
per EIA / JESD51.
TSOP-II
42.96
10.75
FBGA
38.15
9.15
SOJ
25.99
18.8
Unit
°C/W
°C/W
AC Test Loads and Waveforms[4]
10-ns Devices
OUTPUT
Z = 50Ω
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
50 Ω
1.5V
(a)
30 pF*
12-, 15-, 20-ns Devices R 317Ω
3.3V
OUTPUT
30 pF
(b)
3.0V
GND
ALL INPUT PULSES
90%
90%
10%
10%
R2
351Ω
High-Z Characteristics
3.3V
R 317Ω
OUTPUT
5 pF
R2
351Ω
Rise Time: 1 V/ns
(c)
Fall Time: 1 V/ns
(d)
AC Switching Characteristics[5] Over the Operating Range
-10
-12
-15
-20
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Unit
Read Cycle
tpower[6]
VCC(typical) to the first access 100
100
100
100
µs
tRC
Read Cycle Time
10
12
15
20
ns
tAA
Address to Data Valid
10
12
15
20
ns
tOHA
Data Hold from Address Change 3
3
3
3
ns
tACE
CE LOW to Data Valid
10
12
15
20
ns
tDOE
OE LOW to Data Valid
5
6
7
8
ns
tLZOE
tHZOE
tLZCE
tHZCE
OE LOW to Low-Z
OE HIGH to High-Z[7, 8]
CE LOW to Low-Z[8]
CE HIGH to High-Z[7, 8]
0
0
0
0
ns
5
6
7
8
ns
3
3
3
3
ns
5
6
7
8
ns
tPU
CE LOW to Power-Up
0
0
0
0
ns
tPD
CE HIGH to Power-Down
10
12
15
20
ns
tDBE
Byte Enable to Data Valid
5
6
7
8
ns
tLZBE
Byte Enable to Low-Z
0
0
0
0
ns
tHZBE
Byte Disable to High-Z
6
6
7
8
ns
Notes:
4. AC characteristics (except High-Z) for 10-ns parts are tested using the load conditions shown in Figure (a). All other speeds are tested using the Thevenin load
shown in Figure (b). High-Z characteristics are tested for all speeds using the test load shown in Figure (d).
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
6. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed.
7. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage
8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
9. The internal Write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of
either of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the
Write.
Document #: 38-05134 Rev. *H
Page 5 of 12
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