CY7C1041CV33-12ZSXE Просмотр технического описания (PDF) - Cypress Semiconductor

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CY7C1041CV33-12ZSXE

4-Mbit (256 K × 16) Static RAM

Cypress Semiconductor 

CY7C1041CV33 Automotive

Switching Waveforms

Figure 4. Read Cycle No. 1 (Address Transition Controlled)[11, 12]

tRRCC

ADDRESS

DATA OUT

tAA

tOHA

PREVIOUS DATA VALID

DATA VALID

Figure 5. Read Cycle No. 2 (OE Controlled)[12, 13]

ADDRESS

CE

OE

BHE, BLE

DATA OUT

VCC

SUPPLY

CURRENT

tRC

tACE

tDOE

tLZOE

tDBE

tLZBE

HIGH IMPEDANCE

tLZCE

tPU

50%

DATA VALID

tHZOE

tHZCE

tHZBE

HIGH

IMPEDANCE

tPD

ICC

50%

ISB

Notes

11. Device is continuously selected. OE, CE, BHE, and/or BLE = VIL.

12. WE is HIGH for read cycle.

13. Address valid prior to or coincident with CE transition LOW.

Document Number: 001-67307 Rev. *A

Page 8 of 17

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