CY7C1041CV33-15ZXC(2008) Просмотр технического описания (PDF) - Cypress Semiconductor

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CY7C1041CV33-15ZXC
(Rev.:2008)

4-Mbit (256K x 16) Static RAM

Cypress Semiconductor 

CY7C1041CV33

Switching Waveforms (continued)

Figure 6. Write Cycle No. 1 (CE Controlled)[13, 14]

ADDRESS

CE

WE

BHE, BLE

DATA IO

ADDRESS

BHE, BLE

WE

CE

DATA IO

tWC

tSA

tSCE

tAW

tHA

tPWE

tBW

tSD

tHD

Figure 7. Write Cycle No. 2 (BLE or BHE Controlled)

tWC

tSA

tBW

tAW

tHA

tPWE

tSCE

tSD

tHD

Notes

13. Data IO is high impedance if OE, BHE, and/or BLE = VIH.

14. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.

Document Number: 38-05134 Rev. *I

Page 8 of 14

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