CY7C1041CV33-10VI Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C1041CV33-10VI Datasheet PDF : 12 Pages
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CY7C1041CV33
AC Test Loads and Waveforms[11]
8-, 10-ns Devices
OUTPUT
Z = 50Ω
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
50 Ω
1.5V
(a)
30 pF*
3.0V
GND
ALL INPUT PULSES
90%
90%
10%
10%
Rise Time: 1 V/ns
(c)
Switching Waveforms
Fall Time: 1 V/ns
12-, 15-, 20-ns Devices R 317Ω
3.3V
OUTPUT
30 pF
R2
351Ω
(b)
High-Z Characteristics
R 317Ω
3.3V
OUTPUT
5 pF
R2
351Ω
(d)
Read Cycle No. 1[12, 13]
tRC
ADDRESS
DATA OUT
tAA
tOHA
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled) [13, 14]
ADDRESS
tRC
CE
tACE
OE
BHE, BLE
DATA OUT
VCC
SUPPLY
CURRENT
tDOE
tLZOE
tDBE
tLZBE
HIGH IMPEDANCE
tLZCE
tPU
50%
tHZOE
DATA VALID
tHZCE
tHZBE
HIGH
IMPEDANCE
tPD
50%
IICCCC
IISSBB
Notes:
11. AC characteristics (except High-Z) for all 8-ns and 10-ns parts are tested using the load conditions shown in Figure (a). All other speeds are tested using the
Thevenin load shown in Figure (b). High-Z characteristics are tested for all speeds using the test load shown in Figure (d).
12. Device is continuously selected. OE, CE, BHE and/or BHE = VIL.
13. WE is HIGH for Read cycle.
14. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05134 Rev. *E
Page 6 of 12
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