HD74LVC00 Просмотр технического описания (PDF) - Renesas Electronics

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HD74LVC00

Quad. 2-input NAND Gates

Renesas Electronics 

HD74LVC00

Package Dimensions

10.06

10.5 Max

14

8

1

7

1.42 Max

1.27

*0.40 ± 0.06

*Ni/Pd/Au plating

0.15

0.12 M

As of January, 2003

Unit: mm

7.80

+

–

0.20

0.30

1.15

0.70 ± 0.20

0˚ – 8˚

Package Code

JEDEC

JEITA

Mass (reference value)

FP-14DAV

—

Conforms

0.23 g

5.00

5.30 Max

14

8

1

*0.20 ± 0.05

7

0.65

0.13 M

0.83 Max

0.10

As of January, 2003

Unit: mm

1.0

6.40 ± 0.20

0˚ – 8˚ 0.50 ± 0.10

*Ni/Pd/Au plating

Package Code

JEDEC

JEITA

Mass (reference value)

TTP-14DV

—

—

0.05 g

Rev.3.00 Jul. 22, 2004 page 5 of 5

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